Re: [PATCH v2 2/5] hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet

[Philippe Mathieu-Daudé]

Hi Andrew,

On 1/3/21 02:06, Andrew Jeffery wrote:
> The datasheet says we have 197 IRQs allocated, and we need more than 128
> to describe IRQs from LPC devices. Raise the value now to allow
> modelling of the LPC devices.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
>   hw/arm/aspeed_ast2600.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index bc0eeb058b24..22fcb5b0edbe 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
>   
>   #define ASPEED_A7MPCORE_ADDR 0x40460000
>   
> -#define AST2600_MAX_IRQ 128
> +#define AST2600_MAX_IRQ 197

Revisiting this patch (now commit b151de69f6), do we want 197 here or
197 - GIC_INTERNAL = 197 - 32 = 165?

Otherwise this ROUND line from commit 957ad79f73:

  ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),

end requesting a GIC with 256 SPIs, but the A15MPCORE one is limited
to 224...

Hmm I see you name this as 'a7mpcore' but use the A15MPCORE...

    object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
                            TYPE_A15MPCORE_PRIV);

Per [*], A7MPCORE indeed can have up to 480 SPIs.

Maybe we need to implement A7MPCORE along with A15MPCORE but
relaxing the GIC SPIs limit?

[*] 
https://developer.arm.com/documentation/ddi0464/f/Introduction/Configurable-options?lang=en

>   /* Shared Peripheral Interrupt values below are offset by -32 from datasheet 
> */
>   static const int aspeed_soc_ast2600_irqmap[] = {