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[PATCH v3 40/45] Add mailbox property tests. Part 1
|
From: |
Sergey Kambalin |
|
Subject: |
[PATCH v3 40/45] Add mailbox property tests. Part 1 |
|
Date: |
Sun, 3 Dec 2023 18:26:14 -0600 |
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
---
tests/qtest/bcm2838-mailbox.c | 34 ++--
tests/qtest/bcm2838-mailbox.h | 18 +-
tests/qtest/bcm2838-mbox-property-test.c | 206 +++++++++++++++++++++++
tests/qtest/meson.build | 2 +-
4 files changed, 220 insertions(+), 40 deletions(-)
create mode 100644 tests/qtest/bcm2838-mbox-property-test.c
diff --git a/tests/qtest/bcm2838-mailbox.c b/tests/qtest/bcm2838-mailbox.c
index 2edc24e15e..4b160cd56c 100644
--- a/tests/qtest/bcm2838-mailbox.c
+++ b/tests/qtest/bcm2838-mailbox.c
@@ -12,6 +12,10 @@
#include "libqtest-single.h"
#include "bcm2838-mailbox.h"
+REG32(MBOX_EXCHNG_REG, 0)
+FIELD(MBOX_EXCHNG_REG, CHANNEL, 0, 4)
+FIELD(MBOX_EXCHNG_REG, DATA, 4, 28)
+
static uint32_t qtest_mbox0_read_reg32(QTestState *s, uint32_t offset)
{
@@ -25,47 +29,33 @@ static void qtest_mbox1_write_reg32(QTestState *s, uint32_t
offset, uint32_t val
static void qtest_mbox1_write(QTestState *s, uint8_t channel, uint32_t data)
{
- uint32_t reg;
+ uint32_t mbox_reg = 0;
- reg = FIELD_DP32(reg, MBOX_WRITE_REG, CHANNEL, channel);
- reg = FIELD_DP32(reg, MBOX_WRITE_REG, DATA, data);
- qtest_mbox1_write_reg32(s, MBOX_REG_WRITE, reg);
+ mbox_reg = FIELD_DP32(mbox_reg, MBOX_EXCHNG_REG, CHANNEL, channel);
+ mbox_reg = FIELD_DP32(mbox_reg, MBOX_EXCHNG_REG, DATA, data);
+ qtest_mbox1_write_reg32(s, MBOX_REG_WRITE, mbox_reg);
}
int qtest_mbox0_has_data(QTestState *s) {
return !(qtest_mbox0_read_reg32(s, MBOX_REG_STATUS) & MBOX_READ_EMPTY);
}
-int mbox0_has_data(void) {
- return qtest_mbox0_has_data(global_qtest);
-}
-
void qtest_mbox0_read_message(QTestState *s,
uint8_t channel,
void *msgbuf,
size_t msgbuf_size)
{
- uint32_t reg;
+ uint32_t mbox_reg;
uint32_t msgaddr;
g_assert(qtest_mbox0_has_data(s));
- reg = qtest_mbox0_read_reg32(s, MBOX_REG_READ);
- g_assert_cmphex(FIELD_EX32(reg, MBOX_WRITE_REG, CHANNEL), ==, channel);
- msgaddr = FIELD_EX32(reg, MBOX_WRITE_REG, DATA) << 4;
+ mbox_reg = qtest_mbox0_read_reg32(s, MBOX_REG_READ);
+ g_assert_cmphex(FIELD_EX32(mbox_reg, MBOX_EXCHNG_REG, CHANNEL), ==,
channel);
+ msgaddr = FIELD_EX32(mbox_reg, MBOX_EXCHNG_REG, DATA) << 4;
qtest_memread(s, msgaddr, msgbuf, msgbuf_size);
}
-void mbox0_read_message(uint8_t channel, void *msgbuf, size_t msgbuf_size) {
- qtest_mbox0_read_message(global_qtest, channel, msgbuf, msgbuf_size);
-}
-
void qtest_mbox1_write_message(QTestState *s, uint8_t channel, uint32_t
msg_addr)
{
qtest_mbox1_write(s, channel, msg_addr >> 4);
}
-
-
-void mbox1_write_message(uint8_t channel, uint32_t msg_addr)
-{
- qtest_mbox1_write_message(global_qtest, channel, msg_addr);
-}
diff --git a/tests/qtest/bcm2838-mailbox.h b/tests/qtest/bcm2838-mailbox.h
index 2b140a5d32..7e660e65a7 100644
--- a/tests/qtest/bcm2838-mailbox.h
+++ b/tests/qtest/bcm2838-mailbox.h
@@ -77,7 +77,7 @@
#define TAG_SET_GPIO_STATE 0x00038041
#define TAG_INITIALIZE_VCHIQ 0x00048010
-#define BOARD_REVISION 11546898
+#define BOARD_REVISION 0xB03115
#define FIRMWARE_REVISION 346337
#define FIRMWARE_VARIANT 0x77777777 /* TODO: Find the real value */
@@ -147,22 +147,6 @@
/* Used to test stubs that don't perform actual work */
#define DUMMY_VALUE 0x12345678
-REG32(MBOX_WRITE_REG, 0)
-FIELD(MBOX_WRITE_REG, CHANNEL, 0, 4)
-FIELD(MBOX_WRITE_REG, DATA, 4, 28)
-
-REG32(MBOX_SIZE_STAT, 0)
-FIELD(MBOX_SIZE_STAT, SIZE, 0, 30)
-FIELD(MBOX_SIZE_STAT, SUCCESS, 30, 1)
-
-REG32(SET_DEVICE_POWER_STATE_CMD, 0)
-FIELD(SET_DEVICE_POWER_STATE_CMD, EN, 0, 1)
-FIELD(SET_DEVICE_POWER_STATE_CMD, WAIT, 1, 1)
-
-REG32(GET_CLOCK_STATE_CMD, 0)
-FIELD(GET_CLOCK_STATE_CMD, EN, 0, 1)
-FIELD(GET_CLOCK_STATE_CMD, NPRES, 1, 1)
-
typedef struct {
uint32_t size;
uint32_t req_resp_code;
diff --git a/tests/qtest/bcm2838-mbox-property-test.c
b/tests/qtest/bcm2838-mbox-property-test.c
new file mode 100644
index 0000000000..80746dbb95
--- /dev/null
+++ b/tests/qtest/bcm2838-mbox-property-test.c
@@ -0,0 +1,206 @@
+/*
+ * Tests set for BCM2838 mailbox property interface.
+ *
+ * Copyright (c) 2022 Auriga
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/registerfields.h"
+#include "libqtest-single.h"
+#include "bcm2838-mailbox.h"
+
+REG32(MBOX_SIZE_STAT, 0)
+FIELD(MBOX_SIZE_STAT, SIZE, 0, 31)
+FIELD(MBOX_SIZE_STAT, SUCCESS, 31, 1)
+
+REG32(SET_DEVICE_POWER_STATE_CMD, 0)
+FIELD(SET_DEVICE_POWER_STATE_CMD, EN, 0, 1)
+FIELD(SET_DEVICE_POWER_STATE_CMD, WAIT, 1, 1)
+
+REG32(GET_CLOCK_STATE_CMD, 0)
+FIELD(GET_CLOCK_STATE_CMD, EN, 0, 1)
+FIELD(GET_CLOCK_STATE_CMD, NPRES, 1, 1)
+
+#define MBOX_TEST_MESSAGE_ADDRESS 0x10000000
+
+#define TEST_TAG(x) TAG_ ## x
+#define TEST_TAG_TYPE(x) TAG_##x##_t
+
+#define TEST_FN_NAME(test, subtest) \
+ test ## _ ## subtest ## _test
+
+#define SETUP_FN_NAME(test, subtest) \
+ test ## _ ## subtest ## _setup
+
+#define CHECK_FN_NAME(test, subtest) \
+ test ## _ ## subtest ## _spec_check
+
+#define DECLARE_TEST_CASE_SETUP(testname, ...) \
+ void SETUP_FN_NAME(testname, __VA_ARGS__) \
+ (TEST_TAG_TYPE(testname) * tag)
+
+/*----------------------------------------------------------------------------*/
+#define DECLARE_TEST_CASE(testname, ...)
\
+ __attribute__((weak))
\
+ void SETUP_FN_NAME(testname, __VA_ARGS__)
\
+ (TEST_TAG_TYPE(testname) * tag);
\
+ static void CHECK_FN_NAME(testname, __VA_ARGS__)
\
+ (TEST_TAG_TYPE(testname) *tag);
\
+ static void TEST_FN_NAME(testname, __VA_ARGS__)(void) {
\
+ struct {
\
+ MboxBufHeader header;
\
+ TEST_TAG_TYPE(testname) tag;
\
+ uint32_t end_tag;
\
+ } mailbox_buffer = { 0 };
\
+
\
+ QTestState *qts = qtest_init("-machine raspi4b-2g");
\
+
\
+ mailbox_buffer.header.size = sizeof(mailbox_buffer);
\
+ mailbox_buffer.header.req_resp_code = MBOX_PROCESS_REQUEST;
\
+
\
+ mailbox_buffer.tag.id = TEST_TAG(testname);
\
+ mailbox_buffer.tag.value_buffer_size = MAX(
\
+ sizeof(mailbox_buffer.tag.request.value),
\
+ sizeof(mailbox_buffer.tag.response.value));
\
+ mailbox_buffer.tag.request.zero = 0;
\
+
\
+ mailbox_buffer.end_tag = TAG_END;
\
+
\
+ if (SETUP_FN_NAME(testname, __VA_ARGS__)) {
\
+ SETUP_FN_NAME(testname, __VA_ARGS__)(&mailbox_buffer.tag);
\
+ }
\
+
\
+ qtest_memwrite(qts, MBOX_TEST_MESSAGE_ADDRESS,
\
+ &mailbox_buffer, sizeof(mailbox_buffer));
\
+ qtest_mbox1_write_message(qts, MBOX_CHANNEL_ID_PROPERTY,
\
+ MBOX_TEST_MESSAGE_ADDRESS);
\
+
\
+ qtest_mbox0_read_message(qts, MBOX_CHANNEL_ID_PROPERTY,
\
+ &mailbox_buffer, sizeof(mailbox_buffer));
\
+
\
+ g_assert_cmphex(mailbox_buffer.header.req_resp_code, ==,
MBOX_SUCCESS);\
+
\
+ g_assert_cmphex(mailbox_buffer.tag.id, ==, TEST_TAG(testname));
\
+
\
+ uint32_t size = FIELD_EX32(mailbox_buffer.tag.response.size_stat,
\
+ MBOX_SIZE_STAT, SIZE);
\
+ uint32_t success = FIELD_EX32(mailbox_buffer.tag.response.size_stat,
\
+ MBOX_SIZE_STAT, SUCCESS);
\
+ g_assert_cmpint(size, ==, sizeof(mailbox_buffer.tag.response.value));
\
+ g_assert_cmpint(success, ==, 1);
\
+
\
+ CHECK_FN_NAME(testname, __VA_ARGS__)(&mailbox_buffer.tag);
\
+
\
+ qtest_quit(qts);
\
+ }
\
+ static void CHECK_FN_NAME(testname, __VA_ARGS__)
\
+ (TEST_TAG_TYPE(testname) * tag)
+
+/*----------------------------------------------------------------------------*/
+
+#define QTEST_ADD_TEST_CASE(testname, ...)
\
+ qtest_add_func(stringify(/bcm2838/mbox/property/
\
+ TEST_FN_NAME(testname, __VA_ARGS__)-test),
\
+ TEST_FN_NAME(testname, __VA_ARGS__))
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_FIRMWARE_REVISION) {
+ g_assert_cmpint(tag->response.value.revision, ==, FIRMWARE_REVISION);
+}
+
+//
/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_BOARD_REVISION) {
+ g_assert_cmpint(tag->response.value.revision, ==, BOARD_REVISION);
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_ARM_MEMORY) {
+ g_assert_cmphex(tag->response.value.base, ==, ARM_MEMORY_BASE);
+ g_assert_cmphex(tag->response.value.size, ==, ARM_MEMORY_SIZE);
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_VC_MEMORY) {
+ g_assert_cmphex(tag->response.value.base, ==, VC_MEMORY_BASE);
+ g_assert_cmphex(tag->response.value.size, ==, VC_MEMORY_SIZE);
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(SET_DEVICE_POWER_STATE) {
+ uint32_t enabled =
+ FIELD_EX32(tag->response.value.cmd, SET_DEVICE_POWER_STATE_CMD, EN);
+ uint32_t wait =
+ FIELD_EX32(tag->response.value.cmd, SET_DEVICE_POWER_STATE_CMD, WAIT);
+ g_assert_cmphex(tag->response.value.device_id, ==, DEVICE_ID_UART0);
+ g_assert_cmpint(enabled, ==, 1);
+ g_assert_cmpint(wait, ==, 0);
+}
+DECLARE_TEST_CASE_SETUP(SET_DEVICE_POWER_STATE) {
+ tag->request.value.device_id = DEVICE_ID_UART0;
+ tag->response.value.cmd =
+ FIELD_DP32(tag->response.value.cmd, SET_DEVICE_POWER_STATE_CMD, EN, 1);
+ tag->response.value.cmd =
+ FIELD_DP32(tag->response.value.cmd, SET_DEVICE_POWER_STATE_CMD, WAIT,
1);
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_CLOCK_STATE) {
+ uint32_t enabled =
+ FIELD_EX32(tag->response.value.cmd, GET_CLOCK_STATE_CMD, EN);
+ uint32_t not_present =
+ FIELD_EX32(tag->response.value.cmd, GET_CLOCK_STATE_CMD, NPRES);
+ g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_CORE);
+ g_assert_cmphex(enabled, ==, 1);
+ g_assert_cmphex(not_present, ==, 0);
+}
+DECLARE_TEST_CASE_SETUP(GET_CLOCK_STATE) {
+ tag->request.value.clock_id = CLOCK_ID_CORE;
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_CLOCK_RATE, EMMC) {
+ g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_EMMC);
+ g_assert_cmphex(tag->response.value.rate, ==, CLOCK_RATE_EMMC);
+}
+DECLARE_TEST_CASE_SETUP(GET_CLOCK_RATE, EMMC) {
+ tag->request.value.clock_id = CLOCK_ID_EMMC;
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_MAX_CLOCK_RATE, EMMC) {
+ g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_EMMC);
+ g_assert_cmphex(tag->response.value.rate, ==, CLOCK_RATE_EMMC);
+}
+DECLARE_TEST_CASE_SETUP(GET_MAX_CLOCK_RATE, EMMC) {
+ tag->request.value.clock_id = CLOCK_ID_EMMC;
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_MIN_CLOCK_RATE, EMMC) {
+ g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_EMMC);
+ g_assert_cmphex(tag->response.value.rate, ==, CLOCK_RATE_EMMC);
+}
+DECLARE_TEST_CASE_SETUP(GET_MIN_CLOCK_RATE, EMMC) {
+ tag->request.value.clock_id = CLOCK_ID_EMMC;
+}
+
+/*----------------------------------------------------------------------------*/
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+
+ QTEST_ADD_TEST_CASE(GET_FIRMWARE_REVISION);
+ QTEST_ADD_TEST_CASE(GET_BOARD_REVISION);
+ QTEST_ADD_TEST_CASE(GET_ARM_MEMORY);
+ QTEST_ADD_TEST_CASE(GET_VC_MEMORY);
+ QTEST_ADD_TEST_CASE(SET_DEVICE_POWER_STATE);
+ QTEST_ADD_TEST_CASE(GET_CLOCK_STATE);
+ QTEST_ADD_TEST_CASE(GET_CLOCK_RATE, EMMC);
+ QTEST_ADD_TEST_CASE(GET_MAX_CLOCK_RATE, EMMC);
+ QTEST_ADD_TEST_CASE(GET_MIN_CLOCK_RATE, EMMC);
+
+ return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 92eba5ac99..2351e99fd5 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -217,7 +217,7 @@ qtests_aarch64 = \
['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +
\
(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test',
'fuzz-xlnx-dp-test'] : []) + \
(config_all_devices.has_key('CONFIG_XLNX_VERSAL') ? ['xlnx-canfd-test',
'xlnx-versal-trng-test'] : []) + \
- (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test',
'bcm2838-mbox-property-test'] : []) + \
(config_all.has_key('CONFIG_TCG') and
\
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] :
[]) + \
['arm-cpu-features',
--
2.34.1
- [PATCH v3 28/45] Implement GENET register ops, (continued)
- [PATCH v3 28/45] Implement GENET register ops, Sergey Kambalin, 2023/12/03
- [PATCH v3 42/45] Add mailbox property tests. Part 3, Sergey Kambalin, 2023/12/03
- [PATCH v3 32/45] Enable BCM2838 GENET controller, Sergey Kambalin, 2023/12/03
- [PATCH v3 33/45] Connect RNG200, PCIE and GENET to GIC, Sergey Kambalin, 2023/12/03
- [PATCH v3 35/45] Add mailbox test stub, Sergey Kambalin, 2023/12/03
- [PATCH v3 34/45] Add Rpi4b boot tests, Sergey Kambalin, 2023/12/03
- [PATCH v3 37/45] Add mailbox tests tags. Part 1, Sergey Kambalin, 2023/12/03
- [PATCH v3 41/45] Add mailbox property tests. Part 2, Sergey Kambalin, 2023/12/03
- [PATCH v3 38/45] Add mailbox tests tags. Part 2, Sergey Kambalin, 2023/12/03
- [PATCH v3 39/45] Add mailbox tests tags. Part 3, Sergey Kambalin, 2023/12/03
- [PATCH v3 40/45] Add mailbox property tests. Part 1,
Sergey Kambalin <=
- [PATCH v3 43/45] Add missed BCM2835 properties, Sergey Kambalin, 2023/12/03
- [PATCH v3 44/45] Append added properties to mailbox test, Sergey Kambalin, 2023/12/03
- [PATCH v3 45/45] Add RPi4B to paspi4.rst, Sergey Kambalin, 2023/12/03