Re: [PATCH v4 02/10] hw/arm/aspeed_ast27x0 Introduce vbootrom memory region

[Cédric Le Goater]

On 4/17/25 05:11, Jamin Lin wrote:
> Introduce a new vbootrom memory region. The region is mapped at address
> "0x00000000" and has a size of 128KB, identical to the SRAM region size.
> This memory region is intended for loading a vbootrom image file as part of the
> boot process.
>
> The vbootrom registered in the SoC's address space using the ASPEED_DEV_VBOOTROM
> index.
>
> Introduced a "vbootrom_size" attribute in "AspeedSoCClass" to define virtual
> boot ROM size.

Could you please explain why we need a class attribute to size the
vbootrom region ? The rest looks good.


Thanks,

C.



> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> Reviewed-by: Nabih Estefan <nabihestefan@google.com>
> Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
>   include/hw/arm/aspeed_soc.h |  3 +++
>   hw/arm/aspeed_ast27x0.c     | 12 ++++++++++++
>   2 files changed, 15 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index f069d17d16..9af8cfbc3e 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -59,6 +59,7 @@ struct AspeedSoCState {
>       MemoryRegion sram;
>       MemoryRegion spi_boot_container;
>       MemoryRegion spi_boot;
> +    MemoryRegion vbootrom;
>       AddressSpace dram_as;
>       AspeedRtcState rtc;
>       AspeedTimerCtrlState timerctrl;
> @@ -152,6 +153,7 @@ struct AspeedSoCClass {
>       const char * const *valid_cpu_types;
>       uint32_t silicon_rev;
>       uint64_t sram_size;
> +    uint64_t vbootrom_size;
>       uint64_t secsram_size;
>       int spis_num;
>       int ehcis_num;
> @@ -169,6 +171,7 @@ struct AspeedSoCClass {
>   const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
>   
>   enum {
> +    ASPEED_DEV_VBOOTROM,
>       ASPEED_DEV_SPI_BOOT,
>       ASPEED_DEV_IOMEM,
>       ASPEED_DEV_UART0,
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index b05ed75ff4..7eece8e286 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -24,6 +24,7 @@
>   #include "qemu/log.h"
>   
>   static const hwaddr aspeed_soc_ast2700_memmap[] = {
> +    [ASPEED_DEV_VBOOTROM]  =  0x00000000,
>       [ASPEED_DEV_SRAM]      =  0x10000000,
>       [ASPEED_DEV_HACE]      =  0x12070000,
>       [ASPEED_DEV_EMMC]      =  0x12090000,
> @@ -657,6 +658,15 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, 
> Error **errp)
>       memory_region_add_subregion(s->memory,
>                                   sc->memmap[ASPEED_DEV_SRAM], &s->sram);
>   
> +    /* VBOOTROM */
> +    name = g_strdup_printf("aspeed.vbootrom.%d", CPU(&a->cpu[0])->cpu_index);
> +    if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), name,
> +                                sc->vbootrom_size, errp)) {
> +        return;
> +    }
> +    memory_region_add_subregion(s->memory,
> +                                sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
> +
>       /* SCU */
>       if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
>           return;
> @@ -898,6 +908,7 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClass 
> *oc, void *data)
>   
>       sc->valid_cpu_types = valid_cpu_types;
>       sc->silicon_rev  = AST2700_A0_SILICON_REV;
> +    sc->vbootrom_size = 0x20000;
>       sc->sram_size    = 0x20000;
>       sc->spis_num     = 3;
>       sc->wdts_num     = 8;
> @@ -925,6 +936,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass 
> *oc, void *data)
>   
>       sc->valid_cpu_types = valid_cpu_types;
>       sc->silicon_rev  = AST2700_A1_SILICON_REV;
> +    sc->vbootrom_size = 0x20000;
>       sc->sram_size    = 0x20000;
>       sc->spis_num     = 3;
>       sc->wdts_num     = 8;