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[PATCH v7 28/48] nvme: pass request along for tracing
From: |
Klaus Jensen |
Subject: |
[PATCH v7 28/48] nvme: pass request along for tracing |
Date: |
Wed, 15 Apr 2020 07:51:20 +0200 |
From: Klaus Jensen <address@hidden>
Signed-off-by: Klaus Jensen <address@hidden>
Reviewed-by: Maxim Levitsky <address@hidden>
---
hw/block/nvme.c | 67 +++++++++++++++++++++++++------------------
hw/block/trace-events | 2 +-
2 files changed, 40 insertions(+), 29 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 2ff7dd695cd7..66f92f6f6f2d 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -210,14 +210,18 @@ static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList
*qsg, QEMUIOVector *iov,
return NVME_SUCCESS;
}
-static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov, uint64_t prp1,
- uint64_t prp2, uint32_t len, NvmeCtrl *n)
+static uint16_t nvme_map_prp(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
+ uint64_t prp1, uint64_t prp2, uint32_t len,
+ NvmeRequest *req)
{
hwaddr trans_len = n->page_size - (prp1 % n->page_size);
trans_len = MIN(len, trans_len);
int num_prps = (len >> n->page_bits) + 1;
uint16_t status;
+ trace_nvme_dev_map_prp(nvme_cid(req), trans_len, len, prp1, prp2,
+ num_prps);
+
if (unlikely(!prp1)) {
trace_nvme_dev_err_invalid_prp();
return NVME_INVALID_FIELD | NVME_DNR;
@@ -308,13 +312,14 @@ unmap:
}
static uint16_t nvme_dma_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
- uint64_t prp1, uint64_t prp2, DMADirection dir)
+ uint64_t prp1, uint64_t prp2, DMADirection dir,
+ NvmeRequest *req)
{
QEMUSGList qsg;
QEMUIOVector iov;
uint16_t status = NVME_SUCCESS;
- status = nvme_map_prp(&qsg, &iov, prp1, prp2, len, n);
+ status = nvme_map_prp(n, &qsg, &iov, prp1, prp2, len, req);
if (status) {
return status;
}
@@ -559,7 +564,7 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns,
NvmeCmd *cmd,
return NVME_LBA_RANGE | NVME_DNR;
}
- if (nvme_map_prp(&req->qsg, &req->iov, prp1, prp2, data_size, n)) {
+ if (nvme_map_prp(n, &req->qsg, &req->iov, prp1, prp2, data_size, req)) {
block_acct_invalid(blk_get_stats(n->conf.blk), acct);
return NVME_INVALID_FIELD | NVME_DNR;
}
@@ -784,7 +789,7 @@ static uint16_t nvme_smart_info(NvmeCtrl *n, NvmeCmd *cmd,
uint8_t rae,
}
return nvme_dma_prp(n, (uint8_t *) &smart + off, trans_len, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE);
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_fw_log_info(NvmeCtrl *n, NvmeCmd *cmd, uint32_t buf_len,
@@ -804,7 +809,7 @@ static uint16_t nvme_fw_log_info(NvmeCtrl *n, NvmeCmd *cmd,
uint32_t buf_len,
trans_len = MIN(sizeof(fw_log) - off, buf_len);
return nvme_dma_prp(n, (uint8_t *) &fw_log + off, trans_len, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE);
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_error_info(NvmeCtrl *n, NvmeCmd *cmd, uint8_t rae,
@@ -829,7 +834,7 @@ static uint16_t nvme_error_info(NvmeCtrl *n, NvmeCmd *cmd,
uint8_t rae,
trans_len = MIN(sizeof(errlog) - off, buf_len);
return nvme_dma_prp(n, (uint8_t *)&errlog, trans_len, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE);
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_get_log(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
@@ -970,7 +975,8 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
return NVME_SUCCESS;
}
-static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIdentify *c)
+static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIdentify *c,
+ NvmeRequest *req)
{
uint64_t prp1 = le64_to_cpu(c->prp1);
uint64_t prp2 = le64_to_cpu(c->prp2);
@@ -978,10 +984,11 @@ static uint16_t nvme_identify_ctrl(NvmeCtrl *n,
NvmeIdentify *c)
trace_nvme_dev_identify_ctrl();
return nvme_dma_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), prp1,
- prp2, DMA_DIRECTION_FROM_DEVICE);
+ prp2, DMA_DIRECTION_FROM_DEVICE, req);
}
-static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c)
+static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c,
+ NvmeRequest *req)
{
NvmeNamespace *ns;
uint32_t nsid = le32_to_cpu(c->nsid);
@@ -998,10 +1005,11 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n,
NvmeIdentify *c)
ns = &n->namespaces[nsid - 1];
return nvme_dma_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns), prp1,
- prp2, DMA_DIRECTION_FROM_DEVICE);
+ prp2, DMA_DIRECTION_FROM_DEVICE, req);
}
-static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c)
+static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c,
+ NvmeRequest *req)
{
static const int data_len = NVME_IDENTIFY_DATA_SIZE;
uint32_t min_nsid = le32_to_cpu(c->nsid);
@@ -1024,12 +1032,13 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n,
NvmeIdentify *c)
}
}
ret = nvme_dma_prp(n, (uint8_t *)list, data_len, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE);
+ DMA_DIRECTION_FROM_DEVICE, req);
g_free(list);
return ret;
}
-static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeIdentify *c)
+static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeIdentify *c,
+ NvmeRequest *req)
{
uint32_t nsid = le32_to_cpu(c->nsid);
uint64_t prp1 = le64_to_cpu(c->prp1);
@@ -1064,22 +1073,22 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl
*n, NvmeIdentify *c)
stl_be_p(&ns_descrs->uuid.v, nsid);
return nvme_dma_prp(n, list, NVME_IDENTIFY_DATA_SIZE, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE);
+ DMA_DIRECTION_FROM_DEVICE, req);
}
-static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd)
+static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
{
NvmeIdentify *c = (NvmeIdentify *)cmd;
switch (le32_to_cpu(c->cns)) {
case NVME_ID_CNS_NS:
- return nvme_identify_ns(n, c);
+ return nvme_identify_ns(n, c, req);
case NVME_ID_CNS_CTRL:
- return nvme_identify_ctrl(n, c);
+ return nvme_identify_ctrl(n, c, req);
case NVME_ID_CNS_NS_ACTIVE_LIST:
- return nvme_identify_nslist(n, c);
+ return nvme_identify_nslist(n, c, req);
case NVME_ID_CNS_NS_DESCR_LIST:
- return nvme_identify_ns_descr_list(n, c);
+ return nvme_identify_ns_descr_list(n, c, req);
default:
trace_nvme_dev_err_invalid_identify_cns(le32_to_cpu(c->cns));
return NVME_INVALID_FIELD | NVME_DNR;
@@ -1138,7 +1147,8 @@ static inline uint64_t nvme_get_timestamp(const NvmeCtrl
*n)
return cpu_to_le64(ts.all);
}
-static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd)
+static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd,
+ NvmeRequest *req)
{
uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
@@ -1146,7 +1156,7 @@ static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n,
NvmeCmd *cmd)
uint64_t timestamp = nvme_get_timestamp(n);
return nvme_dma_prp(n, (uint8_t *)×tamp, sizeof(timestamp), prp1,
- prp2, DMA_DIRECTION_FROM_DEVICE);
+ prp2, DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
@@ -1198,7 +1208,7 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd
*cmd, NvmeRequest *req)
trace_nvme_dev_getfeat_numq(result);
break;
case NVME_TIMESTAMP:
- return nvme_get_feature_timestamp(n, cmd);
+ return nvme_get_feature_timestamp(n, cmd, req);
case NVME_INTERRUPT_COALESCING:
result = cpu_to_le32(n->features.int_coalescing);
break;
@@ -1224,7 +1234,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd
*cmd, NvmeRequest *req)
return NVME_SUCCESS;
}
-static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd)
+static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd,
+ NvmeRequest *req)
{
uint16_t ret;
uint64_t timestamp;
@@ -1232,7 +1243,7 @@ static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n,
NvmeCmd *cmd)
uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
ret = nvme_dma_prp(n, (uint8_t *)×tamp, sizeof(timestamp), prp1,
- prp2, DMA_DIRECTION_TO_DEVICE);
+ prp2, DMA_DIRECTION_TO_DEVICE, req);
if (ret != NVME_SUCCESS) {
return ret;
}
@@ -1303,7 +1314,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd
*cmd, NvmeRequest *req)
((n->params.max_ioqpairs - 1) << 16));
break;
case NVME_TIMESTAMP:
- return nvme_set_feature_timestamp(n, cmd);
+ return nvme_set_feature_timestamp(n, cmd, req);
case NVME_ASYNCHRONOUS_EVENT_CONF:
n->features.async_config = dw11;
break;
@@ -1357,7 +1368,7 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd,
NvmeRequest *req)
case NVME_ADM_CMD_CREATE_CQ:
return nvme_create_cq(n, cmd);
case NVME_ADM_CMD_IDENTIFY:
- return nvme_identify(n, cmd);
+ return nvme_identify(n, cmd, req);
case NVME_ADM_CMD_ABORT:
return nvme_abort(n, cmd, req);
case NVME_ADM_CMD_SET_FEATURES:
diff --git a/hw/block/trace-events b/hw/block/trace-events
index aff67b52d1e8..e050af87ece4 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -33,7 +33,7 @@ nvme_dev_irq_msix(uint32_t vector) "raising MSI-X IRQ vector
%u"
nvme_dev_irq_pin(void) "pulsing IRQ pin"
nvme_dev_irq_masked(void) "IRQ is masked"
nvme_dev_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=0x%"PRIx64"
prp2=0x%"PRIx64""
-nvme_dev_map_prp(uint16_t cid, uint8_t opc, uint64_t trans_len, uint32_t len,
uint64_t prp1, uint64_t prp2, int num_prps) "cid %"PRIu16" opc 0x%"PRIx8"
trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d"
+nvme_dev_map_prp(uint16_t cid, uint64_t trans_len, uint32_t len, uint64_t
prp1, uint64_t prp2, int num_prps) "cid %"PRIu16" trans_len %"PRIu64" len
%"PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d"
nvme_dev_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode)
"cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8""
nvme_dev_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode) "cid %"PRIu16"
sqid %"PRIu16" opc 0x%"PRIx8""
nvme_dev_rw(const char *verb, uint32_t blk_count, uint64_t byte_count,
uint64_t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64""
--
2.26.0
- [PATCH v7 21/48] nvme: provide the mandatory subnqn field, (continued)
- [PATCH v7 21/48] nvme: provide the mandatory subnqn field, Klaus Jensen, 2020/04/15
- [PATCH v7 30/48] nvme: verify validity of prp lists in the cmb, Klaus Jensen, 2020/04/15
- [PATCH v7 24/48] nvme: add mapping helpers, Klaus Jensen, 2020/04/15
- [PATCH v7 23/48] nvme: memset preallocated requests structures, Klaus Jensen, 2020/04/15
- [PATCH v7 29/48] nvme: add request mapping helper, Klaus Jensen, 2020/04/15
- [PATCH v7 37/48] nvme: add nvme_check_rw helper, Klaus Jensen, 2020/04/15
- [PATCH v7 33/48] nvme: be consistent about zeros vs zeroes, Klaus Jensen, 2020/04/15
- [PATCH v7 32/48] nvme: add check for mdts, Klaus Jensen, 2020/04/15
- [PATCH v7 27/48] nvme: refactor dma read/write, Klaus Jensen, 2020/04/15
- [PATCH v7 31/48] nvme: refactor request bounds checking, Klaus Jensen, 2020/04/15
- [PATCH v7 28/48] nvme: pass request along for tracing,
Klaus Jensen <=
- [PATCH v7 38/48] nvme: use preallocated qsg/iov in nvme_dma_prp, Klaus Jensen, 2020/04/15
- [PATCH v7 34/48] nvme: refactor NvmeRequest, Klaus Jensen, 2020/04/15
- [PATCH v7 35/48] nvme: remove NvmeCmd parameter, Klaus Jensen, 2020/04/15
- [PATCH v7 39/48] pci: pass along the return value of dma_memory_rw, Klaus Jensen, 2020/04/15
- [PATCH v7 40/48] nvme: handle dma errors, Klaus Jensen, 2020/04/15
- [PATCH v7 36/48] nvme: allow multiple aios per command, Klaus Jensen, 2020/04/15
- [PATCH v7 43/48] nvme: add support for sgl bit bucket descriptor, Klaus Jensen, 2020/04/15
- [PATCH v7 47/48] nvme: change controller pci id, Klaus Jensen, 2020/04/15
- [PATCH v7 44/48] nvme: refactor identify active namespace id list, Klaus Jensen, 2020/04/15