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[PATCH v5 16/18] nvme: factor out pmr setup
From: |
Klaus Jensen |
Subject: |
[PATCH v5 16/18] nvme: factor out pmr setup |
Date: |
Tue, 5 May 2020 07:48:38 +0200 |
From: Klaus Jensen <address@hidden>
Signed-off-by: Klaus Jensen <address@hidden>
Reviewed-by: Maxim Levitsky <address@hidden>
---
hw/block/nvme.c | 95 ++++++++++++++++++++++++++-----------------------
1 file changed, 51 insertions(+), 44 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index bd255a5c711a..b0b3d3ffb75f 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -58,6 +58,7 @@
#define NVME_REG_SIZE 0x1000
#define NVME_DB_SIZE 4
#define NVME_CMB_BIR 2
+#define NVME_PMR_BIR 2
#define NVME_GUEST_ERR(trace, fmt, ...) \
do { \
@@ -1459,6 +1460,55 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice
*pci_dev)
PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
}
+static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
+{
+ /* Controller Capabilities register */
+ NVME_CAP_SET_PMRS(n->bar.cap, 1);
+
+ /* PMR Capabities register */
+ n->bar.pmrcap = 0;
+ NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
+ NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
+ NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
+ NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
+ /* Turn on bit 1 support */
+ NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
+ NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
+ NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
+
+ /* PMR Control register */
+ n->bar.pmrctl = 0;
+ NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
+
+ /* PMR Status register */
+ n->bar.pmrsts = 0;
+ NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
+ NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
+ NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
+ NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
+
+ /* PMR Elasticity Buffer Size register */
+ n->bar.pmrebs = 0;
+ NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
+ NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
+ NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
+
+ /* PMR Sustained Write Throughput register */
+ n->bar.pmrswtp = 0;
+ NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
+ NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
+
+ /* PMR Memory Space Control register */
+ n->bar.pmrmsc = 0;
+ NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
+ NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
+
+ pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
+ PCI_BASE_ADDRESS_SPACE_MEMORY |
+ PCI_BASE_ADDRESS_MEM_TYPE_64 |
+ PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
+}
+
static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev)
{
uint8_t *pci_conf = pci_dev->config;
@@ -1537,50 +1587,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error
**errp)
if (n->params.cmb_size_mb) {
nvme_init_cmb(n, pci_dev);
} else if (n->pmrdev) {
- /* Controller Capabilities register */
- NVME_CAP_SET_PMRS(n->bar.cap, 1);
-
- /* PMR Capabities register */
- n->bar.pmrcap = 0;
- NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
- NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
- NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2);
- NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
- /* Turn on bit 1 support */
- NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
- NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
- NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
-
- /* PMR Control register */
- n->bar.pmrctl = 0;
- NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
-
- /* PMR Status register */
- n->bar.pmrsts = 0;
- NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
- NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
- NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
- NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
-
- /* PMR Elasticity Buffer Size register */
- n->bar.pmrebs = 0;
- NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
- NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
- NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
-
- /* PMR Sustained Write Throughput register */
- n->bar.pmrswtp = 0;
- NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
- NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
-
- /* PMR Memory Space Control register */
- n->bar.pmrmsc = 0;
- NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
- NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
-
- pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
- PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
- PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
+ nvme_init_pmr(n, pci_dev);
}
for (i = 0; i < n->num_namespaces; i++) {
--
2.26.2
- [PATCH v5 10/18] nvme: factor out device state setup, (continued)
- [PATCH v5 10/18] nvme: factor out device state setup, Klaus Jensen, 2020/05/05
- [PATCH v5 07/18] nvme: add max_ioqpairs device parameter, Klaus Jensen, 2020/05/05
- [PATCH v5 15/18] nvme: factor out cmb setup, Klaus Jensen, 2020/05/05
- [PATCH v5 14/18] nvme: factor out pci setup, Klaus Jensen, 2020/05/05
- [PATCH v5 09/18] nvme: factor out property/constraint checks, Klaus Jensen, 2020/05/05
- [PATCH v5 11/18] nvme: factor out block backend setup, Klaus Jensen, 2020/05/05
- [PATCH v5 12/18] nvme: add namespace helpers, Klaus Jensen, 2020/05/05
- [PATCH v5 17/18] nvme: do cmb/pmr init as part of pci init, Klaus Jensen, 2020/05/05
- [PATCH v5 13/18] nvme: factor out namespace setup, Klaus Jensen, 2020/05/05
- [PATCH v5 16/18] nvme: factor out pmr setup,
Klaus Jensen <=
- [PATCH v5 18/18] nvme: factor out controller identify setup, Klaus Jensen, 2020/05/05
- Re: [PATCH v5 00/18] nvme: refactoring and cleanups, Philippe Mathieu-Daudé, 2020/05/05
- Re: [PATCH v5 00/18] nvme: refactoring and cleanups, Klaus Jensen, 2020/05/11