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[PATCH 14/22] hw/sd: ssi-sd: Support single block write
From: |
Bin Meng |
Subject: |
[PATCH 14/22] hw/sd: ssi-sd: Support single block write |
Date: |
Thu, 31 Dec 2020 19:30:02 +0800 |
From: Bin Meng <bin.meng@windriver.com>
Add 2 more states for the block write operation. The SPI host needs
to send a data start tocken to start the transfer, and the data block
written to the card will be acknowledged by a data response tocken.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/sd/ssi-sd.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
index 8eb48550cf..21a96e91f0 100644
--- a/hw/sd/ssi-sd.c
+++ b/hw/sd/ssi-sd.c
@@ -42,6 +42,8 @@ typedef enum {
SSI_SD_DATA_START,
SSI_SD_DATA_READ,
SSI_SD_DATA_CRC16,
+ SSI_SD_DATA_WRITE,
+ SSI_SD_SKIP_CRC16,
} ssi_sd_mode;
struct ssi_sd_state {
@@ -52,6 +54,7 @@ struct ssi_sd_state {
uint8_t response[5];
uint16_t crc16;
int32_t read_bytes;
+ int32_t write_bytes;
int32_t arglen;
int32_t response_pos;
int32_t stopping;
@@ -90,6 +93,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD)
/* dummy value - don't care */
#define SSI_DUMMY 0xff
+/* data accepted */
+#define DATA_RESPONSE_ACCEPTED 0x05
+
static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val)
{
ssi_sd_state *s = SSI_SD(dev);
@@ -103,10 +109,17 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev,
uint32_t val)
switch (s->mode) {
case SSI_SD_CMD:
- if (val == SSI_DUMMY) {
+ switch (val) {
+ case SSI_DUMMY:
DPRINTF("NULL command\n");
return SSI_DUMMY;
+ break;
+ case SSI_TOKEN_SINGLE:
+ DPRINTF("Start write block\n");
+ s->mode = SSI_SD_DATA_WRITE;
+ return SSI_DUMMY;
}
+
s->cmd = val & 0x3f;
s->mode = SSI_SD_CMDARG;
s->arglen = 0;
@@ -235,6 +248,27 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev,
uint32_t val)
s->response_pos = 0;
}
return val;
+ case SSI_SD_DATA_WRITE:
+ sdbus_write_byte(&s->sdbus, val);
+ s->write_bytes++;
+ if (!sdbus_receive_ready(&s->sdbus) || s->write_bytes == 512) {
+ DPRINTF("Data write end\n");
+ s->mode = SSI_SD_SKIP_CRC16;
+ s->response_pos = 0;
+ }
+ return val;
+ case SSI_SD_SKIP_CRC16:
+ /* we don't verify the crc16 */
+ s->response_pos++;
+ if (s->response_pos == 2) {
+ DPRINTF("CRC16 receive end\n");
+ s->mode = SSI_SD_RESPONSE;
+ s->write_bytes = 0;
+ s->arglen = 1;
+ s->response[0] = DATA_RESPONSE_ACCEPTED;
+ s->response_pos = 0;
+ }
+ return SSI_DUMMY;
}
/* Should never happen. */
return SSI_DUMMY;
@@ -325,6 +359,7 @@ static void ssi_sd_reset(DeviceState *dev)
memset(s->response, 0, sizeof(s->response));
s->crc16 = 0;
s->read_bytes = 0;
+ s->write_bytes = 0;
s->arglen = 0;
s->response_pos = 0;
s->stopping = 0;
--
2.25.1
- [PATCH 01/22] hw/block: m25p80: Add ISSI SPI flash support, (continued)
- [PATCH 01/22] hw/block: m25p80: Add ISSI SPI flash support, Bin Meng, 2020/12/31
- [PATCH 02/22] hw/block: m25p80: Add various ISSI flash information, Bin Meng, 2020/12/31
- [PATCH 03/22] hw/sd: ssi-sd: Fix incorrect card response sequence, Bin Meng, 2020/12/31
- [PATCH 04/22] hw/sd: sd: Support CMD59 for SPI mode, Bin Meng, 2020/12/31
- [PATCH 05/22] hw/sd: sd: Drop sd_crc16(), Bin Meng, 2020/12/31
- [PATCH 06/22] util: Add CRC16 (CCITT) calculation routines, Bin Meng, 2020/12/31
- [PATCH 07/22] hw/sd: ssi-sd: Suffix a data block with CRC16, Bin Meng, 2020/12/31
- [PATCH 08/22] hw/sd: ssi-sd: Support multiple block read (CMD18), Bin Meng, 2020/12/31
- [PATCH 09/22] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer, Bin Meng, 2020/12/31
- [PATCH 11/22] hw/sd: sd: Allow single/multiple block write for SPI mode, Bin Meng, 2020/12/31
- [PATCH 14/22] hw/sd: ssi-sd: Support single block write,
Bin Meng <=
- [PATCH 10/22] hw/sd: sd: Remove duplicated codes in single/multiple block read/write, Bin Meng, 2020/12/31
- [PATCH 12/22] hw/sd: sd.h: Cosmetic change of using spaces, Bin Meng, 2020/12/31
- [PATCH 13/22] hw/sd: Introduce receive_ready() callback, Bin Meng, 2020/12/31
- [PATCH 15/22] hw/sd: ssi-sd: Support multiple block write, Bin Meng, 2020/12/31
- [PATCH 16/22] hw/ssi: Add SiFive SPI controller support, Bin Meng, 2020/12/31
- [PATCH 18/22] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Bin Meng, 2020/12/31
- [PATCH 19/22] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value, Bin Meng, 2020/12/31
- [PATCH 17/22] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash, Bin Meng, 2020/12/31
- [PATCH 20/22] docs/system: Sort targets in alphabetical order, Bin Meng, 2020/12/31
- [PATCH 21/22] docs/system: Add RISC-V documentation, Bin Meng, 2020/12/31