Re: [SPAM] [PATCH v1 3/8] hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600

[Cédric Le Goater]

On 10/29/24 10:17, Jamin Lin wrote:
> According to the datasheet of AST2600 description, interrupt status set by HW
> and clear to "0" by software writing "1" on the specific bit.
>
> Therefore, if firmware set the specific bit "1" in the interrupt status
> register(0x34), the specific bit of "s->irq_sts" should be cleared 0.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   hw/timer/aspeed_timer.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
> index 5af268ea9e..149f7cc5a6 100644
> --- a/hw/timer/aspeed_timer.c
> +++ b/hw/timer/aspeed_timer.c
> @@ -580,7 +580,7 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState 
> *s, hwaddr offset,
>   
>       switch (offset) {
>       case 0x34:
> -        s->irq_sts &= tv;
> +        s->irq_sts &= ~tv;
>           break;
>       case 0x3C:
>           aspeed_timer_set_ctrl(s, s->ctrl & ~tv);