[Qemu-commits] [qemu/qemu] b55d7d: target/riscv: Allow setting ISA extensions via CPU...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: b55d7d34f6adf7bd246ae2eabf2d66eb5e024a68
      
https://github.com/qemu/qemu/commit/b55d7d34f6adf7bd246ae2eabf2d66eb5e024a68
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Allow setting ISA extensions via CPU props

This patch allows us to enable/disable the RISC-V ISA extensions from
the QEMU command line. This works with the rv32 and rv64 machines. The
idea is that in the future we can now add extensions and leave them
disabled by default until enabled by the user.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b9d1848ebe8f083482307be725cca7883fca7566
      
https://github.com/qemu/qemu/commit/b9d1848ebe8f083482307be725cca7883fca7566
  Author: Nathaniel Graff <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M hw/riscv/sifive_prci.c
    M include/hw/riscv/sifive_prci.h

  Log Message:
  -----------
  sifive_prci: Read and write PRCI registers

Writes to the SiFive PRCI registers are preserved while leaving the
ready bits set for the HFX/HFR oscillators and the lock bit set for the
PLL.

Signed-off-by: Nathaniel Graff <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 49db9fa1fd7c252596b53cf80876e06f407d09ed
      
https://github.com/qemu/qemu/commit/49db9fa1fd7c252596b53cf80876e06f407d09ed
  Author: Dayeol Lee <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: Fix PMP range boundary address bug

A wrong address is passed to `pmp_is_in_range` while checking if a
memory access is within a PMP range.
Since the ending address of the pmp range (i.e., pmp_state.addr[i].ea)
is set to the last address in the range (i.e., pmp base + pmp size - 1),
memory accesses containg the last address in the range will always fail.

For example, assume that a PMP range is 4KB from 0x87654000 such that
the last address within the range is 0x87654fff.
1-byte access to 0x87654fff should be considered to be fully inside the
PMP range.
However the access now fails and complains partial inclusion because
pmp_is_in_range(env, i, addr + size) returns 0 whereas
pmp_is_in_range(env, i, addr) returns 1.

Signed-off-by: Dayeol Lee <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: cbf5827693addaff4e4d2102afedbf078a204eb2
      
https://github.com/qemu/qemu/commit/cbf5827693addaff4e4d2102afedbf078a204eb2
  Author: Michael Clark <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Implement riscv_cpu_unassigned_access

This patch adds support for the riscv_cpu_unassigned_access call
and will raise a load or store access fault.

Signed-off-by: Michael Clark <address@hidden>
[Changes by AF:
 - Squash two patches and rewrite commit message
 - Set baddr to the access address
]
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e0f8fa72deba7ac7a7ae06ba25e6498aaad93ace
      
https://github.com/qemu/qemu/commit/e0f8fa72deba7ac7a7ae06ba25e6498aaad93ace
  Author: Hesham Almatary <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  RISC-V: Only Check PMP if MMU translation succeeds

The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.

For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an instruction fetch page
fault.

This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds. This patch is required for future commits
that properly report PMP exception violations if PTW succeeds.

Signed-off-by: Hesham Almatary <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 635b0b0ea39a13d1a3df932452e5728aebbb3f6e
      
https://github.com/qemu/qemu/commit/635b0b0ea39a13d1a3df932452e5728aebbb3f6e
  Author: Hesham Almatary <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  RISC-V: Raise access fault exceptions on PMP violations

Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations
report "access exceptions." The current PMP implementation has
a bug which wrongly reports "page exceptions" on PMP violations.

This patch fixes this bug by reporting the correct PMP access exceptions
trap values.

Signed-off-by: Hesham Almatary <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: cc0fdb298517ce56c770803447f8b02a90271152
      
https://github.com/qemu/qemu/commit/cc0fdb298517ce56c770803447f8b02a90271152
  Author: Hesham Almatary <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h

  Log Message:
  -----------
  RISC-V: Check for the effective memory privilege mode during PMP checks

The current PMP check function checks for env->priv which is not the effective
memory privilege mode.

For example, mstatus.MPRV could be set while executing in M-Mode, and in that
case the privilege mode for the PMP check should be S-Mode rather than M-Mode
(in env->priv) if mstatus.MPP == PRV_S.

This patch passes the effective memory privilege mode to the PMP check.
Functions that call the PMP check should pass the correct memory privilege mode
after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists).

Suggested-by: Alistair Francis <address@hidden>
Signed-off-by: Hesham Almatary <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 1f447aec787bfbbd078afccae44fc4c92acb4fed
      
https://github.com/qemu/qemu/commit/1f447aec787bfbbd078afccae44fc4c92acb4fed
  Author: Hesham Almatary <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  RISC-V: Check PMP during Page Table Walks

The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.

Suggested-by: Jonathan Behrens <address@hidden>
Signed-off-by: Hesham Almatary <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: f8162068f18f2f264a0355938784f54089234211
      
https://github.com/qemu/qemu/commit/f8162068f18f2f264a0355938784f54089234211
  Author: Hesham Almatary <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off

The current implementation returns 1 (PMP check success) if the address is in
range even if the PMP entry is off. This is a bug.

For example, if there is a PMP check in S-Mode which is in range, but its PMP
entry is off, this will succeed, which it should not.

The patch fixes this bug by only checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.

Signed-off-by: Hesham Almatary <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: db21e6f72721996ddf1948c35a8ee35238089da4
      
https://github.com/qemu/qemu/commit/db21e6f72721996ddf1948c35a8ee35238089da4
  Author: Hesham Almatary <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  RISC-V: Fix a PMP check with the correct access size

The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.

Signed-off-by: Hesham Almatary <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 5b7ae1cec9af5bf96fdc963a52a4595c51b128f9
      
https://github.com/qemu/qemu/commit/5b7ae1cec9af5bf96fdc963a52a4595c51b128f9
  Author: Bin Meng <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv: virt: Correct pci "bus-range" encoding

The largest pci bus number should be calculated from ECAM size,
instead of its base address.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c988de4119af0a0ae7983e870babb5f15793590e
      
https://github.com/qemu/qemu/commit/c988de4119af0a0ae7983e870babb5f15793590e
  Author: Palmer Dabbelt <address@hidden>
  Date:   2019-06-23 (Sun, 23 Jun 2019)

  Changed paths:
    M hw/riscv/sifive_e.c
    M include/hw/riscv/sifive_e.h

  Log Message:
  -----------
  RISC-V: Fix a memory leak when realizing a sifive_e

Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(),
where a pair of recently added MemoryRegion instances would not be freed
if there were errors elsewhere in the function.  The fix here is to
simply not use dynamic allocation for these instances: there's always
one of each in SiFiveESoCState, so instead we just include them within
the struct.

Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt <address@hidden>
Suggested-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: c1fb65e63cfca4506a14b084afd0eca2dc464fe8
      
https://github.com/qemu/qemu/commit/c1fb65e63cfca4506a14b084afd0eca2dc464fe8
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-24 (Mon, 24 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Restructure deprecatd CPUs

Restructure the deprecated CPUs to make it clear in the code that these
are depreated. They are already marked as deprecated in
qemu-deprecated.texi. There are no functional changes.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6729dbbd420696fcf69cf2c86bdfc66e072058ce
      
https://github.com/qemu/qemu/commit/6729dbbd420696fcf69cf2c86bdfc66e072058ce
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-24 (Mon, 24 Jun 2019)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_privileged.inc.c

  Log Message:
  -----------
  target/riscv: Add the privledge spec version 1.11.0

Add support for the ratified RISC-V privledge spec.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 747a43e818dc36bd50ef98c2b11a7c31ceb810fa
      
https://github.com/qemu/qemu/commit/747a43e818dc36bd50ef98c2b11a7c31ceb810fa
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Add the mcountinhibit CSR

1.11 defines mcountinhibit, which has the same numeric CSR value as
mucounteren from 1.09.1 but has different semantics.  This patch enables
the CSR for 1.11-based targets, which is trivial to implement because
the counters in QEMU never tick (legal according to the spec).

Signed-off-by: Alistair Francis <address@hidden>
[Palmer: Fix counter access semantics, change commit message to indicate
the behavior is fully emulated.]
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e3147506b02edcdd7c14ebb41a10fcc3027dcc5c
      
https://github.com/qemu/qemu/commit/e3147506b02edcdd7c14ebb41a10fcc3027dcc5c
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Set privledge spec 1.11.0 as default

Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a101b643c2a74671ffedd50f7a2974937c7a0791
      
https://github.com/qemu/qemu/commit/a101b643c2a74671ffedd50f7a2974937c7a0791
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M qemu-deprecated.texi

  Log Message:
  -----------
  qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1

Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new
1.10.0 and the ratified 1.11.0.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: bdddd44635a7d3b0f746e449ff7a02328bc2b405
      
https://github.com/qemu/qemu/commit/bdddd44635a7d3b0f746e449ff7a02328bc2b405
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Require either I or E base extension

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c9a73910c34a2147bcf6a3b5194d27abb19c2e54
      
https://github.com/qemu/qemu/commit/c9a73910c34a2147bcf6a3b5194d27abb19c2e54
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Remove user version information

Remove the user version information. This was never used and never
publically exposed in a release of QEMU, so let's just remove it. In
future to manage versions we can extend the extension properties to
specify version.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 0a13a5b856ebb59dec6d165b87a0ba0e1e2dd952
      
https://github.com/qemu/qemu/commit/0a13a5b856ebb59dec6d165b87a0ba0e1e2dd952
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Add support for disabling/enabling Counters

Add support for disabling/enabling the "Counters" extension.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 50fba816cd226001bec3e495c39879deb2fa5432
      
https://github.com/qemu/qemu/commit/50fba816cd226001bec3e495c39879deb2fa5432
  Author: Palmer Dabbelt <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Add support for the Zifencei extension

fence.i has been split out of the base ISA as part of the ratification
process.  This patch adds a Zifencei argument, which disables the
fence.i instruction.

Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 591bddea8d874e1500921de0353818e5586618f5
      
https://github.com/qemu/qemu/commit/591bddea8d874e1500921de0353818e5586618f5
  Author: Palmer Dabbelt <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  RISC-V: Add support for the Zicsr extension

The various CSR instructions have been split out of the base ISA as part
of the ratification process.  This patch adds a Zicsr argument, which
disables all the CSR instructions.

Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: c13b169f1a3dd158d6c75727cdc388f95988db39
      
https://github.com/qemu/qemu/commit/c13b169f1a3dd158d6c75727cdc388f95988db39
  Author: Joel Sing <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_helper.c
    M target/riscv/insn_trans/trans_rva.inc.c

  Log Message:
  -----------
  RISC-V: Clear load reservations on context switch and SC

This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.

Signed-off-by: Joel Sing <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ab433cccadb9f8e73bc3350273b049377d54d083
      
https://github.com/qemu/qemu/commit/ab433cccadb9f8e73bc3350273b049377d54d083
  Author: Jim Wilson <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M linux-user/riscv/syscall_nr.h

  Log Message:
  -----------
  RISC-V: Update syscall list for 32-bit support.

32-bit RISC-V uses _llseek instead of lseek as syscall number 62.
Update syscall list from open-embedded build, primarily because
32-bit RISC-V requires statx support.

Tested with cross gcc testsuite runs for rv32 and rv64, with the
pending statx patch also applied.

Signed-off-by: Jim Wilson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 28a4df979a2ef92d9129886cd9dcb00c497ac4cb
      
https://github.com/qemu/qemu/commit/28a4df979a2ef92d9129886cd9dcb00c497ac4cb
  Author: Atish Patra <address@hidden>
  Date:   2019-06-25 (Tue, 25 Jun 2019)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv: virt: Add cpu-topology DT node.

Currently, there is no cpu topology defined in RISC-V.
Define a device tree node that clearly describes the
entire topology. This saves the trouble of scanning individual
cache to figure out the topology.

Here is the linux kernel patch series that enables topology
for RISC-V.

http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html

CPU topology after applying this patch in QEMU & above series in kernel

/ # cat /sys/devices/system/cpu/cpu2/topology/thread_siblings_list
2
/ # cat /sys/devices/system/cpu/cpu2/topology/physical_package_id
0
/ # cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-7

Signed-off-by: Atish Patra <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: f88222dae552c202685f5bee43e6c2e12d3c088c
      
https://github.com/qemu/qemu/commit/f88222dae552c202685f5bee43e6c2e12d3c088c
  Author: Michael Clark <address@hidden>
  Date:   2019-06-27 (Thu, 27 Jun 2019)

  Changed paths:
    M disas/riscv.c

  Log Message:
  -----------
  disas/riscv: Disassemble reserved compressed encodings as illegal

Due to the design of the disassembler, the immediate is not
known during decoding of the opcode; so to handle compressed
encodings with reserved immediate values (non-zero), we need
to add an additional check during decompression to match
reserved encodings with zero immediates and translate them
into the illegal instruction.

The following compressed opcodes have reserved encodings with
zero immediates: c.addi4spn, c.addi, c.lui, c.addi16sp, c.srli,
c.srai, c.andi and c.slli

Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
[Palmer: Broke long lines]
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 2e3df911c5bb8199b72427a36ce68a8fe2decf1f
      
https://github.com/qemu/qemu/commit/2e3df911c5bb8199b72427a36ce68a8fe2decf1f
  Author: Wladimir J. van der Laan <address@hidden>
  Date:   2019-06-27 (Thu, 27 Jun 2019)

  Changed paths:
    M disas/riscv.c

  Log Message:
  -----------
  disas/riscv: Fix `rdinstreth` constraint

The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.

Signed-off-by: Wladimir J. van der Laan <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 382cb4392ff8c3fa911d10da959eb8b0cbee15af
      
https://github.com/qemu/qemu/commit/382cb4392ff8c3fa911d10da959eb8b0cbee15af
  Author: Bin Meng <address@hidden>
  Date:   2019-06-27 (Thu, 27 Jun 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Do not create hard-coded phandles in DT

At present the cpu, plic and ethclk nodes' phandles are hard-coded
to 1/2/3 in DT. If we configure more than 1 cpu for the machine,
all cpu nodes' phandles conflict with each other as they are all 1.
Fix it by removing the hardcode.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 05446f4133ea1fe4b444ba80a823fc1df1a9eeaf
      
https://github.com/qemu/qemu/commit/05446f4133ea1fe4b444ba80a823fc1df1a9eeaf
  Author: Bin Meng <address@hidden>
  Date:   2019-06-27 (Thu, 27 Jun 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Update the plic hart config to support multicore

At present the PLIC is instantiated to support only one hart, while
the machine allows at most 4 harts to be created. When more than 1
hart is configured, PLIC needs to instantiated to support multicore,
otherwise an SMP OS does not work.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 0ac24d56c5e7d32423ea78ac58a06b444d1df04d
      
https://github.com/qemu/qemu/commit/0ac24d56c5e7d32423ea78ac58a06b444d1df04d
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-27 (Thu, 27 Jun 2019)

  Changed paths:
    M hw/riscv/Makefile.objs
    A hw/riscv/boot.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    A include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: Split out the boot functions

Split the common RISC-V boot functions into a seperate file. This allows
us to share the common code.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b30422231b90c089ce73aa4b40461bfdc1be0371
      
https://github.com/qemu/qemu/commit/b30422231b90c089ce73aa4b40461bfdc1be0371
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-27 (Thu, 27 Jun 2019)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: Add support for loading a firmware

Add support for loading a firmware file for the virt machine and the
SiFive U. This can be run with the following command:

    qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel vmlinux

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 395fd69582a00b76a89c12d9c074055a9d207997
      
https://github.com/qemu/qemu/commit/395fd69582a00b76a89c12d9c074055a9d207997
  Author: Alistair Francis <address@hidden>
  Date:   2019-06-27 (Thu, 27 Jun 2019)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  hw/riscv: Extend the kernel loading support

Extend the RISC-V kernel loader to support Image and uImage files.
A Linux kernel can now be booted with:

    qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel Image

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: aff8cee805e5b3c2b6e38ddb85448818a19a48db
      
https://github.com/qemu/qemu/commit/aff8cee805e5b3c2b6e38ddb85448818a19a48db
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M disas/riscv.c
    M hw/riscv/Makefile.objs
    A hw/riscv/boot.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_prci.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    A include/hw/riscv/boot.h
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_prci.h
    M linux-user/riscv/syscall_nr.h
    M qemu-deprecated.texi
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/insn_trans/trans_privileged.inc.c
    M target/riscv/insn_trans/trans_rva.inc.c
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/palmer/tags/riscv-for-master-4.1-sf1-v3' into staging

RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3

This pull request contains a handful of patches that I'd like to target
for the 4.1 soft freeze.  There are a handful of new features:

* Support for the 1.11.0, the latest privileged specification.
* Support for reading and writing the PRCI registers.
* Better control over the ISA of the target machine.
* Support for the cpu-topology device tree node.

Additionally, there are a handful of bug fixes including:

* Load reservations are now broken by both store conditional and by
  scheduling, which fixes issues with parallel applications.
* Various fixes to the PMP implementation.
* Fixes to the 32-bit linux-user syscall ABI.
* Various fixes for instruction decodeing.
* A fix to the PCI device tree "bus-range" property.

This boots 32-bit and 64-bit OpenEmbedded.

Changes since v2 [riscv-for-master-4.1-sf1-v2]:

* Dropped OpenSBI.

Changes since v1 [riscv-for-master-4.1-sf1]:

* Contains a fix to the sifive_u OpenSBI integration.

# gpg: Signature made Wed 03 Jul 2019 09:39:09 BST
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.1-sf1-v3: (32 commits)
  hw/riscv: Extend the kernel loading support
  hw/riscv: Add support for loading a firmware
  hw/riscv: Split out the boot functions
  riscv: sifive_u: Update the plic hart config to support multicore
  riscv: sifive_u: Do not create hard-coded phandles in DT
  disas/riscv: Fix `rdinstreth` constraint
  disas/riscv: Disassemble reserved compressed encodings as illegal
  riscv: virt: Add cpu-topology DT node.
  RISC-V: Update syscall list for 32-bit support.
  RISC-V: Clear load reservations on context switch and SC
  RISC-V: Add support for the Zicsr extension
  RISC-V: Add support for the Zifencei extension
  target/riscv: Add support for disabling/enabling Counters
  target/riscv: Remove user version information
  target/riscv: Require either I or E base extension
  qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
  target/riscv: Set privledge spec 1.11.0 as default
  target/riscv: Add the mcountinhibit CSR
  target/riscv: Add the privledge spec version 1.11.0
  target/riscv: Restructure deprecatd CPUs
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/b2e1bc59f0f1...aff8cee805e5