[Qemu-commits] [qemu/qemu] 51500d: Revert "hw/block/pflash_cfi02: Reduce I/O accesses...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 51500d37700904a0ee1ef775a585d871b36f7060
      
https://github.com/qemu/qemu/commit/51500d37700904a0ee1ef775a585d871b36f7060
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-09 (Tue, 09 Jul 2019)

  Changed paths:
    M hw/block/pflash_cfi02.c

  Log Message:
  -----------
  Revert "hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit"

This reverts commit 3ae0343db69c379beb5750b4ed70794bbed51b85.

Stephen Checkoway noticed commit 3ae0343db69 is incorrect.
This commit state all parallel flashes are limited to 16-bit
accesses, however the x32 configuration exists in some models,
such the Cypress S29CL032J, which CFI Device Geometry Definition
announces:

  CFI ADDR     DATA
  0x28,0x29 = 0x0003 (x32-only asynchronous interface)

Guests should not be affected by the previous change, because
QEMU does not announce itself as x32 capable:

    /* Flash device interface (8 & 16 bits) */
    pfl->cfi_table[0x28] = 0x02;
    pfl->cfi_table[0x29] = 0x00;

Commit 3ae0343db69 does not restrict the bus to 16-bit accesses,
but restrict the implementation as 16-bit access max, so a guest
32-bit access will result in 2x 16-bit calls.

Now, we have 2 boards that register the flash device in 32-bit
access:

- PPC: taihu_405ep

  The CFI id matches the S29AL008J that is a 1MB in x16, while
  the code QEMU forces it to be 2MB, and checking Linux it expects
  a 4MB flash.

- ARM: Digic4

  While the comment says "Samsung K8P3215UQB 64M Bit (4Mx16)",
  this flash is 32Mb (2MB). Also note the CFI id does not match
  the comment.

To avoid unexpected side effect, we revert commit 3ae0343db69,
and will clean the board code later.

Reported-by: Stephen Checkoway <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 7372849f5b77d6c251c4bd3b43626fbfb5bf3aee
      
https://github.com/qemu/qemu/commit/7372849f5b77d6c251c4bd3b43626fbfb5bf3aee
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-09 (Tue, 09 Jul 2019)

  Changed paths:
    M hw/block/pflash_cfi02.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/philmd-gitlab/tags/pflash-next-20190709' into staging

Restore 32-bit I/O accesses on AMD flashes
(precautionary revert).

# gpg: Signature made Tue 09 Jul 2019 16:18:10 BST
# gpg:                using RSA key E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <address@hidden>" 
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/pflash-next-20190709:
  Revert "hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit"

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/8d358a5ea082...7372849f5b77