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[Qemu-commits] [qemu/qemu] 3b0799: softmmu: Tidy dirtylimit_dirty_ring_f
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 3b0799: softmmu: Tidy dirtylimit_dirty_ring_full_time |
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Date: |
Tue, 02 May 2023 04:22:29 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 3b079926769f31c9bdb00e1c8e62103407256563
https://github.com/qemu/qemu/commit/3b079926769f31c9bdb00e1c8e62103407256563
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M softmmu/dirtylimit.c
Log Message:
-----------
softmmu: Tidy dirtylimit_dirty_ring_full_time
Drop inline marker: let compiler decide.
Change return type to uint64_t: this matches the computation in the
return statement and the local variable assignment in the caller.
Rename local to dirty_ring_size_MB to fix typo.
Simplify conversion to MiB via qemu_target_page_bits and right shift.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 58274228f1e8fd8f55d9a684b0342494835ead57
https://github.com/qemu/qemu/commit/58274228f1e8fd8f55d9a684b0342494835ead57
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
When PMP entry overlap part of the page, we'll set the tlb_size to 1, which
will make the address in tlb entry set with TLB_INVALID_MASK, and the next
access will again go through tlb_fill.However, this way will not work in
tb_gen_code() => get_page_addr_code_hostp(): the TLB host address will be
cached, and the following instructions can use this host address directly
which may lead to the bypass of PMP related check.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1542.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230422130329.23555-6-liweiwei@iscas.ac.cn>
Commit: 25cb25861990b4a5dd8b883844724f0e1d3129a2
https://github.com/qemu/qemu/commit/25cb25861990b4a5dd8b883844724f0e1d3129a2
Author: Dickon Hood <dickon.hood@codethink.co.uk>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M include/qemu/bitops.h
Log Message:
-----------
qemu/bitops.h: Limit rotate amounts
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a547ed87b00234bff1757e23b4402fba35230192
https://github.com/qemu/qemu/commit/a547ed87b00234bff1757e23b4402fba35230192
Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M include/qemu/host-utils.h
Log Message:
-----------
qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
This is for use in the RISC-V vclz and vctz instructions (implemented in
proceeding commit).
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-11-lawrence.hunter@codethink.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 77ac798336751697a8e8e5f89962d382f733169f
https://github.com/qemu/qemu/commit/77ac798336751697a8e8e5f89962d382f733169f
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M accel/tcg/tcg-runtime-gvec.c
M accel/tcg/tcg-runtime.h
M include/tcg/tcg-op-gvec.h
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Add tcg_gen_gvec_andcs
Add tcg expander and helper functions for and-compliment
vector with scalar operand.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk>
[rth: Split out of larger patch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 50bec8ac2d2ae213b303fe74710dc3ed166edffe
https://github.com/qemu/qemu/commit/50bec8ac2d2ae213b303fe74710dc3ed166edffe
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M include/tcg/tcg-op-gvec.h
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Add tcg_gen_gvec_rotrs
Add tcg expander and helper functions for rotate right
vector with scalar operand.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk>
[rth: Split out of larger patch; mask rotation count.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 01013d2c10a07bb49da61923dae09968218a520d
https://github.com/qemu/qemu/commit/01013d2c10a07bb49da61923dae09968218a520d
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M tests/qtest/readconfig-test.c
Log Message:
-----------
tests/qtest: Disable the spice test of readconfig-test on FreeBSD
The spice test is currently hanging on FreeBSD. It likely was
never working before, since in the past, our configure script
was failing to detect this feature due to a bug in the spice
package there (it just got enabled recently by the commit
https://cgit.freebsd.org/ports/commit/?id=cf16b1c9063351325f0 ).
To get the CI working again, let's disable the failing test for
now until someone has enough spare time to debug and fix the real
underlying problem.
Message-Id: <20230428151351.1365822-1-thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: b08dc0f1b7b7b3be27ed3ffd72deeb02a1f669e7
https://github.com/qemu/qemu/commit/b08dc0f1b7b7b3be27ed3ffd72deeb02a1f669e7
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG
The test set -accel tcg, so restrict it to when TCG is present.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-Id: <20230426180013.14814-13-farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 7915bd06f25e1803778081161bf6fa10c42dc7cd
https://github.com/qemu/qemu/commit/7915bd06f25e1803778081161bf6fa10c42dc7cd
Author: Alexander Bulekov <alxndr@bu.edu>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M util/async.c
Log Message:
-----------
async: avoid use-after-free on re-entrancy guard
A BH callback can free the BH, causing a use-after-free in aio_bh_call.
Fix that by keeping a local copy of the re-entrancy guard pointer.
Buglink: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=58513
Fixes: 9c86c97f12 ("async: Add an optional reentrancy guard to the BH API")
Signed-off-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20230501141956.3444868-1-alxndr@bu.edu>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 67055d0d88c84ca5bee9386aebb8ca61b8aa8042
https://github.com/qemu/qemu/commit/67055d0d88c84ca5bee9386aebb8ca61b8aa8042
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M include/qemu/int128.h
Log Message:
-----------
qemu/int128: Re-shuffle Int128Alias members
Clang 14, with --enable-tcg-interpreter errors with
include/qemu/int128.h:487:16: error: alignment of field 'i' (128 bits)
does not match the alignment of the first field in transparent union;
transparent_union attribute ignored [-Werror,-Wignored-attributes]
__int128_t i;
^
include/qemu/int128.h:486:12: note: alignment of first field is 64 bits
Int128 s;
^
1 error generated.
By placing the __uint128_t member first, this is avoided.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230501204625.277361-1-richard.henderson@linaro.org>
Commit: b416e3b856970b3aef37eaa7c6121fa2cc7bfbe6
https://github.com/qemu/qemu/commit/b416e3b856970b3aef37eaa7c6121fa2cc7bfbe6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M meson.build
M migration/xbzrle.c
Log Message:
-----------
migration/xbzrle: Use __attribute__((target)) for avx512
Use the attribute, which is supported by clang, instead of
the #pragma, which is not supported and, for some reason,
also not detected by the meson probe, so we fail by -Werror.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20230501210555.289806-1-richard.henderson@linaro.org>
Commit: 8a6ede0912d4ed979323f137a82ca649fd178f53
https://github.com/qemu/qemu/commit/8a6ede0912d4ed979323f137a82ca649fd178f53
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M include/exec/cpu_ldst.h
Log Message:
-----------
accel/tcg: Add cpu_ld*_code_mmu
At least RISC-V has the need to be able to perform a read
using execute permissions, outside of translation.
Add helpers to facilitate this.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-9-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-9-richard.henderson@linaro.org>
Commit: 6887ff02da66c8084b8bc0934c0f845bfd04ce3c
https://github.com/qemu/qemu/commit/6887ff02da66c8084b8bc0934c0f845bfd04ce3c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
Since TCG_TYPE_I32 values are kept sign-extended in registers,
via ".w" instructions, we need not extend if the register matches.
This is already relied upon by comparisons.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7f98ec2115ef8c911bcd45a85cca0f7873478912
https://github.com/qemu/qemu/commit/7f98ec2115ef8c911bcd45a85cca0f7873478912
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Conditionalize tcg_out_exts_i32_i64
Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not
extend if the register matches. This is already relied upon by comparisons.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: bdc7fba1c5a29ae218b45353daac9308fe1aae82
https://github.com/qemu/qemu/commit/bdc7fba1c5a29ae218b45353daac9308fe1aae82
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/tcg.c
Log Message:
-----------
tcg: Introduce tcg_out_movext2
This is common code in most qemu_{ld,st} slow paths, moving two
registers when there may be overlap between sources and destinations.
At present, this is only used by 32-bit hosts for 64-bit data,
but will shortly be used for more than that.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b5f47ba73b7c1457d2f18d71c00e1a91a76fe60b
https://github.com/qemu/qemu/commit/b5f47ba73b7c1457d2f18d71c00e1a91a76fe60b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M tests/qtest/meson.build
M tests/qtest/readconfig-test.c
M util/async.c
Log Message:
-----------
Merge tag 'pull-request-2023-05-02' of https://gitlab.com/thuth/qemu into
staging
* Fix the failing FreeBSD job in our CI
* Run the tpm-tis-i2c-test only if TCG is enabled
* Fix a use-after-free problem in the new reentracy checking code
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# gpg: Signature made Tue 02 May 2023 11:16:17 AM BST
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2023-05-02' of https://gitlab.com/thuth/qemu:
async: avoid use-after-free on re-entrancy guard
tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG
tests/qtest: Disable the spice test of readconfig-test on FreeBSD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1b0e90a87b46cde63d0394f1dffa2a2a819c0501
https://github.com/qemu/qemu/commit/1b0e90a87b46cde63d0394f1dffa2a2a819c0501
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/tcg-runtime-gvec.c
M accel/tcg/tcg-runtime.h
M accel/tcg/user-exec.c
M include/exec/cpu_ldst.h
M include/qemu/bitops.h
M include/qemu/host-utils.h
M include/qemu/int128.h
M include/tcg/tcg-op-gvec.h
M meson.build
M migration/xbzrle.c
M softmmu/dirtylimit.c
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/tcg-op-gvec.c
M tcg/tcg.c
Log Message:
-----------
Merge tag 'pull-tcg-20230502' of https://gitlab.com/rth7680/qemu into staging
Misc tcg-related patch queue.
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[ultimate]
* tag 'pull-tcg-20230502' of https://gitlab.com/rth7680/qemu:
tcg: Introduce tcg_out_movext2
tcg/mips: Conditionalize tcg_out_exts_i32_i64
tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
accel/tcg: Add cpu_ld*_code_mmu
migration/xbzrle: Use __attribute__((target)) for avx512
qemu/int128: Re-shuffle Int128Alias members
tcg: Add tcg_gen_gvec_rotrs
tcg: Add tcg_gen_gvec_andcs
qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
qemu/bitops.h: Limit rotate amounts
accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
softmmu: Tidy dirtylimit_dirty_ring_full_time
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/7c18f2d66352...1b0e90a87b46
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