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[Qemu-commits] [qemu/qemu] fc2622: Hexagon (target/hexagon) Add support
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] fc2622: Hexagon (target/hexagon) Add support for v68/v69/v... |
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Date: |
Fri, 19 May 2023 07:54:07 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: fc2622f660fea5355565a6734c74f68e65953ac8
https://github.com/qemu/qemu/commit/fc2622f660fea5355565a6734c74f68e65953ac8
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M configure
M linux-user/hexagon/target_elf.h
M target/hexagon/README
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M tests/tcg/hexagon/Makefile.target
M tests/tcg/hexagon/misc.c
Log Message:
-----------
Hexagon (target/hexagon) Add support for v68/v69/v71/v73
Add support for the ELF flags
Move target/hexagon/cpu.[ch] to be v73
Change the compiler flag used by "make check-tcg"
The decbin instruction is removed in Hexagon v73, so check the
version before trying to compile the instruction.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-2-tsimpson@quicinc.com>
Commit: 406c74f22d457969bdc0b604876d671211cbdaa9
https://github.com/qemu/qemu/commit/406c74f22d457969bdc0b604876d671211cbdaa9
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/gen_tcg.h
M target/hexagon/imported/encode_pp.def
M target/hexagon/imported/ldst.idef
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) Add v68 scalar instructions
The following instructions are added
L2_loadw_aq
L4_loadd_aq
R6_release_at_vi
R6_release_st_vi
S2_storew_rl_at_vi
S4_stored_rl_at_vi
S2_storew_rl_st_vi
S4_stored_rl_st_vi
The release instructions are nop's in qemu. The others behave as
loads/stores.
The encodings for these instructions changed some "don't care" bits
L2_loadw_locked
L4_loadd_locked
S2_storew_locked
S4_stored_locked
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-3-tsimpson@quicinc.com>
Commit: 860132e29543c6ab747745ceeed875593a355d1f
https://github.com/qemu/qemu/commit/860132e29543c6ab747745ceeed875593a355d1f
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/v68_scalar.c
Log Message:
-----------
Hexagon (tests/tcg/hexagon) Add v68 scalar tests
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-4-tsimpson@quicinc.com>
Commit: f128c0fe10a64c69c78b7c41e8ba0991e1761ae1
https://github.com/qemu/qemu/commit/f128c0fe10a64c69c78b7c41e8ba0991e1761ae1
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/imported/mmvec/encode_ext.def
M target/hexagon/imported/mmvec/ext.idef
M target/hexagon/mmvec/macros.h
Log Message:
-----------
Hexagon (target/hexagon) Add v68 HVX instructions
The following instructions are added
V6_v6mpyvubs10_vxx
V6_v6mpyhubs10_vxx
V6_v6mpyvubs10
V6_v6mpyhubs10
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-5-tsimpson@quicinc.com>
Commit: d636fb70b26ba2f712008a6deafeef55a8fd0a9c
https://github.com/qemu/qemu/commit/d636fb70b26ba2f712008a6deafeef55a8fd0a9c
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/v68_hvx.c
A tests/tcg/hexagon/v6mpy_ref.c.inc
Log Message:
-----------
Hexagon (tests/tcg/hexagon) Add v68 HVX tests
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-6-tsimpson@quicinc.com>
Commit: b2f20c2c509df87a408b27f1117549177b31410e
https://github.com/qemu/qemu/commit/b2f20c2c509df87a408b27f1117549177b31410e
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/gen_tcg_hvx.h
M target/hexagon/imported/mmvec/encode_ext.def
M target/hexagon/imported/mmvec/ext.idef
Log Message:
-----------
Hexagon (target/hexagon) Add v69 HVX instructions
The following instructions are added
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-7-tsimpson@quicinc.com>
Commit: 6c61d4e138a3fb67ca443bb8017ac4049d5457a2
https://github.com/qemu/qemu/commit/6c61d4e138a3fb67ca443bb8017ac4049d5457a2
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/v69_hvx.c
Log Message:
-----------
Hexagon (tests/tcg/hexagon) Add v69 HVX tests
The following instructions are tested
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-8-tsimpson@quicinc.com>
Commit: 59958d8903fbf03209a3f62e36708de969d09a1a
https://github.com/qemu/qemu/commit/59958d8903fbf03209a3f62e36708de969d09a1a
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/gen_tcg.h
M target/hexagon/imported/branch.idef
M target/hexagon/imported/encode_pp.def
Log Message:
-----------
Hexagon (target/hexagon) Add v73 scalar instructions
The following instructions are added
J2_callrh
J2_junprh
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-9-tsimpson@quicinc.com>
Commit: 4dd311ed2ee695a86ea77281c20dbeb115403d21
https://github.com/qemu/qemu/commit/4dd311ed2ee695a86ea77281c20dbeb115403d21
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/v73_scalar.c
Log Message:
-----------
Hexagon (tests/tcg/hexagon) Add v73 scalar tests
Tests added for the following instructions
J2_callrh
J2_jumprh
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-10-tsimpson@quicinc.com>
Commit: 63efb6ab5601762a40a739f97328be69b6b89561
https://github.com/qemu/qemu/commit/63efb6ab5601762a40a739f97328be69b6b89561
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M meson.build
Log Message:
-----------
meson.build Add CONFIG_HEXAGON_IDEF_PARSER
Enable conditional compilation depending on whether idef-parser
is configured
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-2-tsimpson@quicinc.com>
Commit: 07540a28c7ecc5fb8cbb0522f3cdead5bcd6d191
https://github.com/qemu/qemu/commit/07540a28c7ecc5fb8cbb0522f3cdead5bcd6d191
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/README
M target/hexagon/gen_tcg.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/idef-parser/parser-helpers.c
Log Message:
-----------
Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write
Add DisasContext arg to gen_log_reg_write_pair also
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-3-tsimpson@quicinc.com>
Commit: 17fda3c2d4064c82fa29e83561e0fb6ae8673c16
https://github.com/qemu/qemu/commit/17fda3c2d4064c82fa29e83561e0fb6ae8673c16
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
Log Message:
-----------
Hexagon (target/hexagon) Add overrides for loop setup instructions
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-4-tsimpson@quicinc.com>
Commit: 085b6700f0063c4702706ac4bdcb80931b74e307
https://github.com/qemu/qemu/commit/085b6700f0063c4702706ac4bdcb80931b74e307
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
Log Message:
-----------
Hexagon (target/hexagon) Add overrides for allocframe/deallocframe
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-5-tsimpson@quicinc.com>
Commit: 5c4b11e827e3cd64a6790b6158c75ed876e6f6e9
https://github.com/qemu/qemu/commit/5c4b11e827e3cd64a6790b6158c75ed876e6f6e9
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/macros.h
Log Message:
-----------
Hexagon (target/hexagon) Add overrides for clr[tf]new
These instructions have implicit reads from p0, so we don't want
them in helpers when idef-parser is off.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-6-tsimpson@quicinc.com>
Commit: 9942f6a8b66a9fc320fadc52c0f72fcfaebf5b50
https://github.com/qemu/qemu/commit/9942f6a8b66a9fc320fadc52c0f72fcfaebf5b50
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M target/hexagon/op_helper.h
Log Message:
-----------
Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch]
With the overrides added in prior commits, this function is not used
Remove references in macros.h
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-7-tsimpson@quicinc.com>
Commit: d24f0b2b89d0f4f595a1b62c00c4c951d1d5fce9
https://github.com/qemu/qemu/commit/d24f0b2b89d0f4f595a1b62c00c4c951d1d5fce9
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
M target/hexagon/helper.h
M target/hexagon/macros.h
M target/hexagon/op_helper.c
Log Message:
-----------
Hexagon (target/hexagon) Eliminate uses of log_pred_write function
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
The following instructions are overriden
S2_cabacdecbin
SA1_cmpeqi
Remove the log_pred_write function from op_helper.c
Remove references in macros.h
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-8-tsimpson@quicinc.com>
Commit: 25e1d87d1041a27c1f34480b53059faeb6600fef
https://github.com/qemu/qemu/commit/25e1d87d1041a27c1f34480b53059faeb6600fef
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/genptr.c
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) Clean up pred_written usage
Only endloop instructions will conditionally write to a predicate.
When there is an endloop instruction, we preload the values into
new_pred_value.
The only place pred_written is needed is when HEX_DEBUG is on.
We remove the last use of check_for_attrib. However, new uses will be
introduced later in this series, so we mark it with G_GNUC_UNUSED.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-9-tsimpson@quicinc.com>
Commit: 71ed3697250e284e353b7abe05f667c5d6b9bc1b
https://github.com/qemu/qemu/commit/71ed3697250e284e353b7abe05f667c5d6b9bc1b
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/genptr.c
Log Message:
-----------
Hexagon (target/hexagon) Don't overlap dest writes with source reads
When generating TCG, make sure we have read all the operand registers
before writing to the destination registers.
This is a prerequesite for short-circuiting where the source and dest
operands could be the same.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-10-tsimpson@quicinc.com>
Commit: b9f0326bf7f584227dd10cbf5222e49130c7fc86
https://github.com/qemu/qemu/commit/b9f0326bf7f584227dd10cbf5222e49130c7fc86
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/hex_common.py
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Mark registers as read during packet analysis
Have gen_analyze_funcs mark the registers that are read by the
instruction. We also mark the implicit reads using instruction
attributes.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-11-tsimpson@quicinc.com>
Commit: d54c56156f409344f8cf232f1e7ee68defa811b9
https://github.com/qemu/qemu/commit/d54c56156f409344f8cf232f1e7ee68defa811b9
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/arch.c
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M target/hexagon/gen_helper_funcs.py
M target/hexagon/gen_helper_protos.py
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/gen_tcg.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/helper.h
M target/hexagon/hex_common.py
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Short-circuit packet register writes
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->need_commit to helpers when needed.
Finally, we can early-exit from gen_reg_writes during packet commit.
There are a few instructions whose semantics write to the result before
reading all the inputs. Therefore, the idef-parser generated code is
incompatible with short-circuit. We tell idef-parser to skip them.
For debugging purposes, we add a cpu property to turn off short-circuit.
When the short-circuit property is false, we skip the analysis and force
the end-of-packet commit.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
BEFORE:
---- 004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
---- 004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
Commit: 455e169d7cad4499ed9f4647215b9ec71aa706e4
https://github.com/qemu/qemu/commit/455e169d7cad4499ed9f4647215b9ec71aa706e4
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) Short-circuit packet predicate writes
In certain cases, we can avoid the overhead of writing to hex_new_pred_value
and write directly to hex_pred. We consider predicate reads/writes when
computing ctx->need_commit. The get_result_pred() function uses this
field to decide between hex_new_pred_value and hex_pred. Then, we can
early-exit from gen_pred_writes.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-13-tsimpson@quicinc.com>
Commit: b85529854ee1a67a1169683a4446f2500a9c14c9
https://github.com/qemu/qemu/commit/b85529854ee1a67a1169683a4446f2500a9c14c9
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/genptr.c
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) Short-circuit packet HVX writes
In certain cases, we can avoid the overhead of writing to future_VRegs
and write directly to VRegs. We consider HVX reads/writes when computing
ctx->need_commit. Then, we can early-exit from gen_commit_hvx.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-14-tsimpson@quicinc.com>
Commit: d05d5eebc77f607f96e582527e43908a274b2abf
https://github.com/qemu/qemu/commit/d05d5eebc77f607f96e582527e43908a274b2abf
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/gen_tcg_hvx.h
M target/hexagon/translate.c
M target/hexagon/translate.h
M tests/tcg/hexagon/hvx_misc.c
Log Message:
-----------
Hexagon (target/hexagon) Short-circuit more HVX single instruction packets
The generated helpers for HVX use pass-by-reference, so they can't
short-circuit when the reads/writes overlap. The instructions with
overrides are OK because they use tcg_gen_gvec_*.
We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs
to set the flag when the instruction is an HVX instruction with a
generated helper.
We add an override for V6_vcombine so that it can be short-circuited
along with a test case in tests/tcg/hexagon/hvx_misc.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-15-tsimpson@quicinc.com>
Commit: 00e64fda061ba65668a19dd1ea79e2a2f72090da
https://github.com/qemu/qemu/commit/00e64fda061ba65668a19dd1ea79e2a2f72090da
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/read_write_overlap.c
Log Message:
-----------
Hexagon (target/hexagon) Add overrides for disabled idef-parser insns
The following have overrides
S2_insert
S2_insert_rp
S2_asr_r_svw_trun
A2_swiz
These instructions have semantics that write to the destination
before all the operand reads have been completed. Therefore,
the idef-parser versions were disabled with the short-circuit patch.
Test cases added to tests/tcg/hexagon/read_write_overlap.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-16-tsimpson@quicinc.com>
Commit: 6aa4f1d15ca8f843d92cf8e431a03d5b1278054c
https://github.com/qemu/qemu/commit/6aa4f1d15ca8f843d92cf8e431a03d5b1278054c
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/README
M target/hexagon/cpu.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/macros.h
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Make special new_value for USR
Precursor to moving new_value from the global state to DisasContext
USR will need to stay in the global state because some helpers will
set it's value
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-17-tsimpson@quicinc.com>
Commit: 4ff5676474cff9afd02c4755d97b0438e764f9d9
https://github.com/qemu/qemu/commit/4ff5676474cff9afd02c4755d97b0438e764f9d9
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/cpu.h
M target/hexagon/genptr.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move new_value to DisasContext
The new_value array in the CPUHexagonState is only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-18-tsimpson@quicinc.com>
Commit: e22edc7c1df59607dea3cf3d8529097ae38e3ae0
https://github.com/qemu/qemu/commit/e22edc7c1df59607dea3cf3d8529097ae38e3ae0
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/cpu.h
M target/hexagon/gen_tcg.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/idef-parser/parser-helpers.c
M target/hexagon/op_helper.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move new_pred_value to DisasContext
The new_pred_value array in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-19-tsimpson@quicinc.com>
Commit: 842b206f268a69d7def87b990f272a514c49837b
https://github.com/qemu/qemu/commit/842b206f268a69d7def87b990f272a514c49837b
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/cpu.h
M target/hexagon/genptr.c
M target/hexagon/helper.h
M target/hexagon/op_helper.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move pred_written to DisasContext
The pred_written variable in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-20-tsimpson@quicinc.com>
Commit: e5d0d78db4adc76200d9d8c3f055176911b42c5d
https://github.com/qemu/qemu/commit/e5d0d78db4adc76200d9d8c3f055176911b42c5d
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/cpu.h
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/gen_helper_funcs.py
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/hex_common.py
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M target/hexagon/op_helper.h
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext
The pkt_has_store_s1 field is only used for bookkeeping helpers with
a load. With recent changes that eliminate the need to free TCGv
variables, it makes more sense to make this transient.
These helpers already take the instruction slot as an argument. We
combine the slot and pkt_has_store_s1 into a single argument called
slotval.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-21-tsimpson@quicinc.com>
Commit: 0fc56c437566f15e3fe54b568951eecb3cd68bf3
https://github.com/qemu/qemu/commit/0fc56c437566f15e3fe54b568951eecb3cd68bf3
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/README
M target/hexagon/cpu.h
M target/hexagon/genptr.c
M target/hexagon/helper.h
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move items to DisasContext
The following items in the CPUHexagonState are only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
The following items are moved
dczero_addr
branch_taken
this_PC
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-22-tsimpson@quicinc.com>
Commit: 163e5fa38e47281f8e83946794f6c202749bff32
https://github.com/qemu/qemu/commit/163e5fa38e47281f8e83946794f6c202749bff32
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/idef-parser/idef-parser.lex
M target/hexagon/idef-parser/idef-parser.y
M target/hexagon/idef-parser/parser-helpers.c
M target/hexagon/idef-parser/parser-helpers.h
M tests/tcg/hexagon/fpstuff.c
M tests/tcg/hexagon/misc.c
Log Message:
-----------
Hexagon (target/hexagon) Additional instructions handled by idef-parser
**** Changes in v3 ****
Fix bugs exposed by dpmpyss_rnd_s0 instruction
Set correct size/signedness for constants
Test cases added to tests/tcg/hexagon/misc.c
**** Changes in v2 ****
Fix bug in imm_print identified in clang build
Currently, idef-parser skips all floating point instructions. However,
there are some floating point instructions that can be handled.
The following instructions are now parsed
F2_sfimm_p
F2_sfimm_n
F2_dfimm_p
F2_dfimm_n
F2_dfmpyll
F2_dfmpylh
To make these instructions work, we fix some bugs in parser-helpers.c
gen_rvalue_extend
gen_cast_op
imm_print
lexer properly sets size/signedness of constants
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230501203125.4025991-1-tsimpson@quicinc.com>
Commit: 4354f3dbae3acf6a2116be361e4c497896270518
https://github.com/qemu/qemu/commit/4354f3dbae3acf6a2116be361e4c497896270518
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/idef-parser/idef-parser.y
M target/hexagon/idef-parser/parser-helpers.c
Log Message:
-----------
target/hexagon: fix = vs. == mishap
**** Changes in v2 ****
Fix yyassert's for sign and zero extends
Coverity reports a parameter that is "set but never used". This is caused
by an assignment operator being used instead of equality.
Co-authored-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Tested-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230428204411.1400931-1-tsimpson@quicinc.com>
Commit: c3199390c2357f5bf695fa0cbf2b1cfd48ebc5fc
https://github.com/qemu/qemu/commit/c3199390c2357f5bf695fa0cbf2b1cfd48ebc5fc
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/gen_helper_funcs.py
M target/hexagon/gen_helper_protos.py
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/hex_common.py
Log Message:
-----------
Hexagon (target/hexagon/*.py): raise exception on reg parsing error
Currently, the python scripts used for the hexagon building will not
abort the compilation when there is an error parsing a register. Let's
make the compilation properly fail in such cases by rasing an exception
instead of just printing a warning message, which might get lost in the
output.
This patch was generated with:
git grep -l "Bad register" *hexagon* | \
xargs sed -i "" -e 's/print("Bad register parse: "[,
]*\([^)]*\))/hex_common.bad_register(\1)/g'
Plus the bad_register() helper added to hex_common.py.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<1f5dbd92f68fdd89e2647e4ba527a2c32cf0f070.1683217043.git.quic_mathbern@quicinc.com>
Commit: f0e0c9844326d47694299e1d9ce3c0bcc1b3a457
https://github.com/qemu/qemu/commit/f0e0c9844326d47694299e1d9ce3c0bcc1b3a457
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/cpu.c
M target/hexagon/cpu.h
Log Message:
-----------
Hexagon: list available CPUs with `-cpu help`
Currently, qemu-hexagon only models the v67 cpu. Nonetheless if we try
to get this information with `-cpu help`, qemu just exists with an error
code and no output. Let's correct that.
The code is basically a copy from target/alpha/cpu.h, but we strip the
"-hexagon-cpu" suffix before printing. This is to avoid confusing
situations like the following:
$ qemu-hexagon -cpu help
Available CPUs:
v67-hexagon-cpu
$ qemu-hexagon -cpu v67-hexagon-cpu ./prog
qemu-hexagon: unable to find CPU model 'v67-hexagon-cpu'
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<b946e17c7e17eed9095700b54c5ead36e5d55dfa.1683225804.git.quic_mathbern@quicinc.com>
Commit: 3128588232333beb505505366133d18da671e2c8
https://github.com/qemu/qemu/commit/3128588232333beb505505366133d18da671e2c8
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M linux-user/hexagon/target_elf.h
Log Message:
-----------
Hexagon: append eflags to unknown cpu model string
Running qemu-hexagon with a binary that was compiled for an arch version
unknown by qemu can produce a somewhat confusing message:
qemu-hexagon: unable to find CPU model 'unknown'
Let's give a bit more info by appending the eflags so that the message
becomes:
qemu-hexagon: unable to find CPU model 'unknown (0x69)'
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<8a8d013cc619b94fd4fb577ae6a8df26cedb972b.1683225804.git.quic_mathbern@quicinc.com>
Commit: ed9b28fb009a7944fcda89c3ced3cb6ad4a92ea1
https://github.com/qemu/qemu/commit/ed9b28fb009a7944fcda89c3ced3cb6ad4a92ea1
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/iclass.c
Log Message:
-----------
Hexagon (iclass): update J4_hintjumpr slot constraints
The Hexagon PRM says that "The assembler automatically encodes
instructions in the packet in the proper order. In the binary encoding
of a packet, the instructions must be ordered from Slot 3 down to
Slot 0."
Prior to the architecture version v73, the slot constraints from
instruction "hintjr" only allowed it to be executed at slot 2.
With that in mind, consider the packet:
{
hintjr(r0)
nop
nop
if (!p0) memd(r1+#0) = r1:0
}
To satisfy the ordering rule quoted from the PRM, the assembler would,
thus, move one of the nops to the first position, so that it can be
assigned to slot 3 and the subsequent hintjr to slot 2.
However, since v73, hintjr can be executed at either slot 2 or 3. So
there is no need to reorder that packet and the assembler will encode it
as is. When QEMU tries to execute it, however, we end up hitting a
"misaliged store" exception because both the store and the hintjr will
be assigned to store 0, and some functions like `slot_is_predicated()`
expect the decode machinery to assign only one instruction per slot. In
particular, the mentioned function will traverse the packet until it
finds the first instruction at the desired slot which, for slot 0, will
be hintjr. Since hintjr is not predicated, the result is that we try to
execute the store regardless of the predicate. And because the predicate
is false, we had not previously loaded hex_store_addr[0] or
hex_store_width[0]. As a result, the store will decide de width based on
trash memory, causing it to be misaligned.
Update the slot constraints for hintjr so that QEMU can properly handle
such encodings.
Note: to avoid similar-but-not-identical issues in the future, we should
look for multiple instructions at the same slot during decoding time and
throw an invalid packet exception. That will be done in the subsequent
commit.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<0fcd8293642c6324119fbbab44741164bcbd04fb.1673616964.git.quic_mathbern@quicinc.com>
Commit: 14edcf11e297252c995d5909144f3751b7383efc
https://github.com/qemu/qemu/commit/14edcf11e297252c995d5909144f3751b7383efc
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/decode.c
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/invalid-slots.c
Log Message:
-----------
Hexagon (decode): look for pkts with multiple insns at the same slot
Each slot in a packet can be assigned to at most one instruction.
Although the assembler generally ought to enforce this rule, we better
be safe than sorry and also do some check to properly throw an "invalid
packet" exception on wrong slot assignments.
This should also make it easier to debug possible future errors caused
by missing updates to `find_iclass_slots()` rules in
target/hexagon/iclass.c.
Co-authored-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<f8b829443523568823d062adf8bf6659bc6d4a3f.1683552984.git.quic_mathbern@quicinc.com>
Commit: 9e6d4938d106ca775108ec2a1fecc6d789543088
https://github.com/qemu/qemu/commit/9e6d4938d106ca775108ec2a1fecc6d789543088
Author: Marco Liebel <quic_mliebel@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M tests/tcg/hexagon/hvx_misc.c
Log Message:
-----------
Remove test_vshuff from hvx_misc tests
test_vshuff checks that the vshuff instruction works correctly when
both vector registers are the same. Using vshuff in this way is
undefined and will be rejected by the compiler in a future version of
the toolchain.
Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20230509184231.2467626-1-quic_mliebel@quicinc.com>
Commit: 758370052fb602f9f23c3b8ae26a6133373c78e6
https://github.com/qemu/qemu/commit/758370052fb602f9f23c3b8ae26a6133373c78e6
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M gdbstub/gdbstub.c
M gdbstub/internals.h
M gdbstub/softmmu.c
M gdbstub/user.c
Log Message:
-----------
gdbstub: only send stop-reply packets when allowed to
GDB's remote serial protocol allows stop-reply messages to be sent by
the stub either as a notification packet or as a reply to a GDB command
(provided that the cmd accepts such a response). QEMU currently does not
implement notification packets, so it should only send stop-replies
synchronously and when requested. Nevertheless, it still issues
unsolicited stop messages through gdb_vm_state_change().
Although this behavior doesn't seem to cause problems with GDB itself
(the messages are just ignored), it can impact other debuggers that
implement the GDB remote serial protocol, like hexagon-lldb. Let's
change the gdbstub to send stop messages only as a response to a
previous GDB command that accepts such a reply.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<a49c0897fc22a6a7827c8dfc32aef2e1d933ec6b.1683214375.git.quic_mathbern@quicinc.com>
Commit: dae66a3f669eaf0e33447ed42a36ad4ee2f178f2
https://github.com/qemu/qemu/commit/dae66a3f669eaf0e33447ed42a36ad4ee2f178f2
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M tests/guest-debug/run-test.py
M tests/tcg/multiarch/system/Makefile.softmmu-target
Log Message:
-----------
gdbstub: add test for untimely stop-reply packets
In the previous commit, we modified gdbstub.c to only send stop-reply
packets as a response to GDB commands that accept it. Now, let's add a
test for this intended behavior. Running this test before the fix from
the previous commit fails as QEMU sends a stop-reply packet
asynchronously, when GDB was in fact waiting an ACK.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<a30d93b9a8d66e9d9294354cfa2fc3af35f00202.1683214375.git.quic_mathbern@quicinc.com>
Commit: ab930e80097c8b3472717363435cee8363e55152
https://github.com/qemu/qemu/commit/ab930e80097c8b3472717363435cee8363e55152
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M MAINTAINERS
M configs/targets/hexagon-linux-user.mak
A gdb-xml/hexagon-core.xml
M target/hexagon/cpu.c
Log Message:
-----------
Hexagon: add core gdbstub xml data for LLDB
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<d25a3a79334d81f0e1ecfb438b6ee82585d02dc4.1683214375.git.quic_mathbern@quicinc.com>
Commit: b0bd9d8adff1b4e967e1cd4c42d82a9d46712cbd
https://github.com/qemu/qemu/commit/b0bd9d8adff1b4e967e1cd4c42d82a9d46712cbd
Author: Brian Cain <bcain@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M target/hexagon/gdbstub.c
Log Message:
-----------
Hexagon (gdbstub): fix p3:0 read and write via stub
Signed-off-by: Brian Cain <bcain@quicinc.com>
Co-authored-by: Sid Manning <sidneym@quicinc.com>
Signed-off-by: Sid Manning <sidneym@quicinc.com>
Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<32e7de567cdae184a6781644454bbb19916c955b.1683214375.git.quic_mathbern@quicinc.com>
Commit: b647652ee5f9bc16a431cc2dbd8525b371b3cb1b
https://github.com/qemu/qemu/commit/b647652ee5f9bc16a431cc2dbd8525b371b3cb1b
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M configs/targets/hexagon-linux-user.mak
A gdb-xml/hexagon-hvx.xml
M target/hexagon/cpu.c
M target/hexagon/gdbstub.c
M target/hexagon/internal.h
Log Message:
-----------
Hexagon (gdbstub): add HVX support
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Co-authored-by: Brian Cain <bcain@quicinc.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id:
<17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathbern@quicinc.com>
Commit: 9073bfd725440da0af44f1ee1e3bcf72e9de39b6
https://github.com/qemu/qemu/commit/9073bfd725440da0af44f1ee1e3bcf72e9de39b6
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M linux-user/hexagon/cpu_loop.c
Log Message:
-----------
Hexagon (linux-user/hexagon): handle breakpoints
This enables LLDB to work with hexagon linux-user mode through the GDB
remote protocol.
Helped-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<c287a129dcbe7d974d8b7608e8672d34a3c91c04.1683214375.git.quic_mathbern@quicinc.com>
Commit: 449d6d9eb44772e69f11d002e3c1e2be8a91c350
https://github.com/qemu/qemu/commit/449d6d9eb44772e69f11d002e3c1e2be8a91c350
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-18 (Thu, 18 May 2023)
Changed paths:
M MAINTAINERS
M configs/targets/hexagon-linux-user.mak
M configure
A gdb-xml/hexagon-core.xml
A gdb-xml/hexagon-hvx.xml
M gdbstub/gdbstub.c
M gdbstub/internals.h
M gdbstub/softmmu.c
M gdbstub/user.c
M linux-user/hexagon/cpu_loop.c
M linux-user/hexagon/target_elf.h
M meson.build
M target/hexagon/README
M target/hexagon/arch.c
M target/hexagon/attribs_def.h.inc
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M target/hexagon/decode.c
M target/hexagon/gdbstub.c
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/gen_helper_funcs.py
M target/hexagon/gen_helper_protos.py
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/gen_tcg.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/gen_tcg_hvx.h
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/helper.h
M target/hexagon/hex_common.py
M target/hexagon/iclass.c
M target/hexagon/idef-parser/idef-parser.lex
M target/hexagon/idef-parser/idef-parser.y
M target/hexagon/idef-parser/parser-helpers.c
M target/hexagon/idef-parser/parser-helpers.h
M target/hexagon/imported/branch.idef
M target/hexagon/imported/encode_pp.def
M target/hexagon/imported/ldst.idef
M target/hexagon/imported/mmvec/encode_ext.def
M target/hexagon/imported/mmvec/ext.idef
M target/hexagon/internal.h
M target/hexagon/macros.h
M target/hexagon/mmvec/macros.h
M target/hexagon/op_helper.c
M target/hexagon/op_helper.h
M target/hexagon/translate.c
M target/hexagon/translate.h
M tests/guest-debug/run-test.py
M tests/tcg/hexagon/Makefile.target
M tests/tcg/hexagon/fpstuff.c
M tests/tcg/hexagon/hvx_misc.c
A tests/tcg/hexagon/invalid-slots.c
M tests/tcg/hexagon/misc.c
A tests/tcg/hexagon/read_write_overlap.c
A tests/tcg/hexagon/v68_hvx.c
A tests/tcg/hexagon/v68_scalar.c
A tests/tcg/hexagon/v69_hvx.c
A tests/tcg/hexagon/v6mpy_ref.c.inc
A tests/tcg/hexagon/v73_scalar.c
M tests/tcg/multiarch/system/Makefile.softmmu-target
Log Message:
-----------
Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into staging
Hexagon update
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# gpg: Signature made Thu 18 May 2023 12:48:24 PM PDT
# gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422
* tag 'pull-hex-20230518-1' of https://github.com/quic/qemu: (44 commits)
Hexagon (linux-user/hexagon): handle breakpoints
Hexagon (gdbstub): add HVX support
Hexagon (gdbstub): fix p3:0 read and write via stub
Hexagon: add core gdbstub xml data for LLDB
gdbstub: add test for untimely stop-reply packets
gdbstub: only send stop-reply packets when allowed to
Remove test_vshuff from hvx_misc tests
Hexagon (decode): look for pkts with multiple insns at the same slot
Hexagon (iclass): update J4_hintjumpr slot constraints
Hexagon: append eflags to unknown cpu model string
Hexagon: list available CPUs with `-cpu help`
Hexagon (target/hexagon/*.py): raise exception on reg parsing error
target/hexagon: fix = vs. == mishap
Hexagon (target/hexagon) Additional instructions handled by idef-parser
Hexagon (target/hexagon) Move items to DisasContext
Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext
Hexagon (target/hexagon) Move pred_written to DisasContext
Hexagon (target/hexagon) Move new_pred_value to DisasContext
Hexagon (target/hexagon) Move new_value to DisasContext
Hexagon (target/hexagon) Make special new_value for USR
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/146f515110e8...449d6d9eb447
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