[Qemu-commits] [qemu/qemu] bbb025: fsl-imx6: Add SNVS support for i.MX6 boards

[Richard Henderson]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: bbb02509f2fece730350620a429276143a1e2232
      
https://github.com/qemu/qemu/commit/bbb02509f2fece730350620a429276143a1e2232
  Author: Vitaly Cheptsov <cheptsov@ispras.ru>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/fsl-imx6.c
    M include/hw/arm/fsl-imx6.h

  Log Message:
  -----------
  fsl-imx6: Add SNVS support for i.MX6 boards

SNVS is supported on both i.MX6 and i.MX6UL and is needed
to support shutdown on the board.

Cc: Peter Maydell <peter.maydell@linaro.org> (odd fixer:SABRELITE / i.MX6)
Cc: Jean-Christophe Dubois <jcd@tribudubois.net> (reviewer:SABRELITE / i.MX6)
Cc: qemu-arm@nongnu.org (open list:SABRELITE / i.MX6)
Cc: qemu-devel@nongnu.org (open list:All patches CC here)
Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru>
Message-id: 20230515095015.66860-1-cheptsov@ispras.ru
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 263d0e48672c552c97cdbdbe2105d7b9fd0b133c
      
https://github.com/qemu/qemu/commit/263d0e48672c552c97cdbdbe2105d7b9fd0b133c
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/smmuv3-internal.h

  Log Message:
  -----------
  hw/arm/smmuv3: Add missing fields for IDR0

In preparation for adding stage-2 support.
Add IDR0 fields related to stage-2.

VMID16: 16-bit VMID supported.
S2P: Stage-2 translation supported.

They are described in 6.3.1 SMMU_IDR0.

No functional change intended.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-2-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3b736c61849ebc16776143a947a90a731b0aea55
      
https://github.com/qemu/qemu/commit/3b736c61849ebc16776143a947a90a731b0aea55
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmuv3: Update translation config to hold stage-2

In preparation for adding stage-2 support, add a S2 config
struct(SMMUS2Cfg), composed of the following fields and embedded in
the main SMMUTransCfg:
 -tsz: Size of IPA input region (S2T0SZ)
 -sl0: Start level of translation (S2SL0)
 -affd: AF Fault Disable (S2AFFD)
 -record_faults: Record fault events (S2R)
 -granule_sz: Granule page shift (based on S2TG)
 -vmid: Virtual Machine ID (S2VMID)
 -vttb: Address of translation table base (S2TTB)
 -eff_ps: Effective PA output range (based on S2PS)

They will be used in the next patches in stage-2 address translation.

The fields in SMMUS2Cfg, are reordered to make the shared and stage-1
fields next to each other, this reordering didn't change the struct
size (104 bytes before and after).

Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas.
oas is stage-1 output address size. However, it is used to check
input address in case stage-1 is unimplemented or bypassed according
to SMMUv3 manual IHI0070.E "3.4. Address sizes"

Shared fields: stage, disabled, bypassed, aborted, iotlb_*.

No functional change intended.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-3-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bcc919e756cd793e59038f59ad69d543b369f689
      
https://github.com/qemu/qemu/commit/bcc919e756cd793e59038f59ad69d543b369f689
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3.c
    M hw/arm/trace-events
    M include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmuv3: Refactor stage-1 PTW

In preparation for adding stage-2 support, rename smmu_ptw_64 to
smmu_ptw_64_s1 and refactor some of the code so it can be reused in
stage-2 page table walk.

Remove AA64 check from PTW as decode_cd already ensures that AA64 is
used, otherwise it faults with C_BAD_CD.

A stage member is added to SMMUPTWEventInfo to differentiate
between stage-1 and stage-2 ptw faults.

Add stage argument to trace_smmu_ptw_level be consistent with other
trace events.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-4-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e703f7076a255cd13b1d9fc0934480a613614f14
      
https://github.com/qemu/qemu/commit/e703f7076a255cd13b1d9fc0934480a613614f14
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/smmu-internal.h

  Log Message:
  -----------
  hw/arm/smmuv3: Add page table walk for stage-2

In preparation for adding stage-2 support, add Stage-2 PTW code.
Only Aarch64 format is supported as stage-1.

Nesting stage-1 and stage-2 is not supported right now.

HTTU is not supported, SW is expected to maintain the Access flag.
This is described in the SMMUv3 manual(IHI 0070.E.a)
"5.2. Stream Table Entry" in "[181] S2AFFD".
This flag determines the behavior on access of a stage-2 page whose
descriptor has AF == 0:
- 0b0: An Access flag fault occurs (stall not supported).
- 0b1: An Access flag fault never occurs.
An Access fault takes priority over a Permission fault.

There are 3 address size checks for stage-2 according to
(IHI 0070.E.a) in "3.4. Address sizes".
- As nesting is not supported, input address is passed directly to
stage-2, and is checked against IAS.
We use cfg->oas to hold the OAS when stage-1 is not used, this is set
in the next patch.
This check is done outside of smmu_ptw_64_s2 as it is not part of
stage-2(it throws stage-1 fault), and the stage-2 function shouldn't
change it's behavior when nesting is supported.
When nesting is supported and we figure out how to combine TLB for
stage-1 and stage-2 we can move this check into the stage-1 function
as described in ARM DDI0487I.a in pseudocode
aarch64/translation/vmsa_translation/AArch64.S1Translate
aarch64/translation/vmsa_translation/AArch64.S1DisabledOutput

- Input to stage-2 is checked against s2t0sz, and throws stage-2
transaltion fault if exceeds it.

- Output of stage-2 is checked against effective PA output range.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-5-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ed1a07adbd3aa47cb884d0008be8a0385100e552
      
https://github.com/qemu/qemu/commit/ed1a07adbd3aa47cb884d0008be8a0385100e552
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M include/hw/arm/smmu-common.h
    M include/hw/arm/smmuv3.h

  Log Message:
  -----------
  hw/arm/smmuv3: Parse STE config for stage-2

Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
Validity of field values are checked when possible.

Only AA64 tables are supported and Small Translation Tables (STT) are
not supported.

According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields
with an S2 prefix (with the exception of S2VMID) are IGNORED when
stage-2 bypasses translation (Config[1] == 0).

Which means that VMID can be used(for TLB tagging) even if stage-2 is
bypassed, so we parse it unconditionally when S2P exists. Otherwise
it is set to -1.(only S1P)

As stall is not supported, if S2S is set the translation would abort.
For S2R, we reuse the same code used for stage-1 with flag
record_faults. However when nested translation is supported we would
need to separate stage-1 and stage-2 faults.

Fix wrong shift in STE_S2HD, STE_S2HA, STE_S2S.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230516203327.2051088-6-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0154688d03cbd65f74bf28a12d46714fd5e007b5
      
https://github.com/qemu/qemu/commit/0154688d03cbd65f74bf28a12d46714fd5e007b5
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/smmuv3.c

  Log Message:
  -----------
  hw/arm/smmuv3: Make TLB lookup work for stage-2

Right now, either stage-1 or stage-2 are supported, this simplifies
how we can deal with TLBs.
This patch makes TLB lookup work if stage-2 is enabled instead of
stage-1.
TLB lookup is done before a PTW, if a valid entry is found we won't
do the PTW.
To be able to do TLB lookup, we need the correct tagging info, as
granularity and input size, so we get this based on the supported
translation stage. The TLB entries are added correctly from each
stage PTW.

When nested translation is supported, this would need to change, for
example if we go with a combined TLB implementation, we would need to
use the min of the granularities in TLB.

As stage-2 shouldn't be tagged by ASID, it will be set to -1 if S1P
is not enabled.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-7-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cb68e2dcaf25cb4dabc18770564076a2998ef591
      
https://github.com/qemu/qemu/commit/cb68e2dcaf25cb4dabc18770564076a2998ef591
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/smmu-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/trace-events
    M include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmuv3: Add VMID to TLB tagging

Allow TLB to be tagged with VMID.

If stage-1 is only supported, VMID is set to -1 and ignored from STE
and CMD_TLBI_NH* cmds.

Update smmu_iotlb_insert trace event to have vmid.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-8-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 58b521562b56ae0d0f1de8705515a2ef2c70d972
      
https://github.com/qemu/qemu/commit/58b521562b56ae0d0f1de8705515a2ef2c70d972
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3.c
    M hw/arm/trace-events
    M include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmuv3: Add CMDs related to stage-2

CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
same as CMD_TLBI_NH_VAA.

CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.

For stage-1 only commands, add a check to throw CERROR_ILL if used
when stage-1 is not supported.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-9-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e3026bff8212a92ea2b6bd597ea70cfc1f029556
      
https://github.com/qemu/qemu/commit/e3026bff8212a92ea2b6bd597ea70cfc1f029556
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/smmuv3.c
    M hw/arm/trace-events

  Log Message:
  -----------
  hw/arm/smmuv3: Add stage-2 support in iova notifier

In smmuv3_notify_iova, read the granule based on translation stage
and use VMID if valid value is sent.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-10-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 51adb602a24a1b22bfe4c4ef92d1881444c04b1b
      
https://github.com/qemu/qemu/commit/51adb602a24a1b22bfe4c4ef92d1881444c04b1b
  Author: Mostafa Saleh <smostafa@google.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/smmuv3.c
    M include/hw/arm/smmuv3.h

  Log Message:
  -----------
  hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2

As everything is in place, we can use a new system property to
advertise which stage is supported and remove bad_ste from STE
stage2 config.

The property added arm-smmuv3.stage can have 3 values:
- "1": Stage-1 only is advertised.
- "2": Stage-2 only is advertised.

If not passed or an unsupported value is passed, it will default to
stage-1.

Advertise VMID16.

Don't try to decode CD, if stage-2 is configured.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-11-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e96f7177262cea9a6a19e23cb72d473a90c7a793
      
https://github.com/qemu/qemu/commit/e96f7177262cea9a6a19e23cb72d473a90c7a793
  Author: Tommy Wu <tommy.wu@sifive.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/dma/xilinx_axidma.c

  Log Message:
  -----------
  hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.

When we receive a packet from the xilinx_axienet and then try to s2mem
through the xilinx_axidma, if the descriptor ring buffer is full in the
xilinx axidma driver, we’ll assert the DMASR.HALTED in the
function : stream_process_s2mem and return 0. In the end, we’ll be stuck in
an infinite loop in axienet_eth_rx_notify.

This patch checks the DMASR.HALTED state when we try to push data
from xilinx axi-enet to xilinx axi-dma. When the DMASR.HALTED is asserted,
we will not keep pushing the data and then prevent the infinte loop.

Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20230519062137.1251741-1-tommy.wu@sifive.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2d0891d8bdc9bdd4fdb7304286a61655a48db21a
      
https://github.com/qemu/qemu/commit/2d0891d8bdc9bdd4fdb7304286a61655a48db21a
  Author: Clément Chigot <chigot@adacore.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number

When passing --smp with a number lower than XLNX_ZYNQMP_NUM_APU_CPUS,
the expression (ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS) will result
in a positive number as ms->smp.cpus is a unsigned int.
This will raise the following error afterwards, as Qemu will try to
instantiate some additional RPUs.
  | $ qemu-system-aarch64 --smp 1 -M xlnx-zcu102
  | **
  | ERROR:../src/tcg/tcg.c:777:tcg_register_thread:
  |   assertion failed: (n < tcg_max_ctxs)

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20230524143714.565792-1-chigot@adacore.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d825dd9193cacbd19512e2735193dc0806411f18
      
https://github.com/qemu/qemu/commit/d825dd9193cacbd19512e2735193dc0806411f18
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M tests/qtest/meson.build

  Log Message:
  -----------
  tests/qtest: Run arm-specific tests only if the required machine is available

pflash-cfi02-test.c always uses the "musicpal" machine for testing,
test-arm-mptimer.c always uses the "vexpress-a9" machine, and
microbit-test.c requires the "microbit" machine, so we should only
run these tests if the machines have been enabled in the configuration.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230524080600.1618137-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 973b9398f5c27cbda6b78cb2ad47d9a367e6798e
      
https://github.com/qemu/qemu/commit/973b9398f5c27cbda6b78cb2ad47d9a367e6798e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M target/arm/tcg/tlb_helper.c

  Log Message:
  -----------
  target/arm: Explicitly select short-format FSR for M-profile

For M-profile, there is no guest-facing A-profile format FSR, but we
still use the env->exception.fsr field to pass fault information from
the point where a fault is raised to the code in
arm_v7m_cpu_do_interrupt() which interprets it and sets the M-profile
specific fault status registers.  So it doesn't matter whether we
fill in env->exception.fsr in the short format or the LPAE format, as
long as both sides agree.  As it happens arm_v7m_cpu_do_interrupt()
assumes short-form.

In compute_fsr_fsc() we weren't explicitly choosing short-form for
M-profile, but instead relied on it falling out in the wash because
arm_s1_regime_using_lpae_format() would be false.  This was broken in
commit 452c67a4 when we added v8R support, because we said "PMSAv8 is
always LPAE format" (as it is for v8R), forgetting that we were
implicitly using this code path on M-profile. At that point we would
hit a g_assert_not_reached():
 ERROR:../../target/arm/internals.h:549:arm_fi_to_lfsc: code should not be 
reached

#7  0x0000555555e055f7 in arm_fi_to_lfsc (fi=0x7fffecff9a90) at 
../../target/arm/internals.h:549
#8  0x0000555555e05a27 in compute_fsr_fsc (env=0x555557356670, 
fi=0x7fffecff9a90, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff9a1c)
    at ../../target/arm/tlb_helper.c:95
#9  0x0000555555e05b62 in arm_deliver_fault (cpu=0x555557354800, 
addr=268961344, access_type=MMU_INST_FETCH, mmu_idx=1, fi=0x7fffecff9a90)
    at ../../target/arm/tlb_helper.c:132
#10 0x0000555555e06095 in arm_cpu_tlb_fill (cs=0x555557354800, 
address=268961344, size=1, access_type=MMU_INST_FETCH, mmu_idx=1, probe=false, 
retaddr=0)
    at ../../target/arm/tlb_helper.c:260

The specific assertion changed when commit fcc7404eff24b4c added
"assert not M-profile" to arm_is_secure_below_el3(), because the
conditions being checked in compute_fsr_fsc() include
arm_el_is_aa64(), which will end up calling arm_is_secure_below_el3()
and asserting before we try to call arm_fi_to_lfsc():

#7  0x0000555555efaf43 in arm_is_secure_below_el3 (env=0x5555574665a0) at 
../../target/arm/cpu.h:2396
#8  0x0000555555efb103 in arm_is_el2_enabled (env=0x5555574665a0) at 
../../target/arm/cpu.h:2448
#9  0x0000555555efb204 in arm_el_is_aa64 (env=0x5555574665a0, el=1) at 
../../target/arm/cpu.h:2509
#10 0x0000555555efbdfd in compute_fsr_fsc (env=0x5555574665a0, 
fi=0x7fffecff99e0, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff996c)

Avoid the assertion and the incorrect FSR format selection by
explicitly making M-profile use the short-format in this function.

Fixes: 452c67a42704 ("target/arm: Enable TTBCR_EAE for ARMv8-R AArch32")a
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1658
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230523131726.866635-1-peter.maydell@linaro.org


  Commit: 3250bf943b9d32461e8d5a74e950b66c11a0e722
      
https://github.com/qemu/qemu/commit/3250bf943b9d32461e8d5a74e950b66c11a0e722
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M target/arm/Kconfig

  Log Message:
  -----------
  target/arm: Explain why we need to select ARM_V7M

We currently need to select ARM_V7M unconditionally when TCG is
present in the build because some translate.c helpers and the whole of
m_helpers.c are not yet under CONFIG_ARM_V7M.

Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230523180525.29994-2-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dd5bc03d5b72040aa44bc9b8a3e69fd3a3955114
      
https://github.com/qemu/qemu/commit/dd5bc03d5b72040aa44bc9b8a3e69fd3a3955114
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M configs/devices/aarch64-softmmu/default.mak
    M configs/devices/arm-softmmu/default.mak

  Log Message:
  -----------
  arm/Kconfig: Keep Kconfig default entries in default.mak as documentation

When we moved the arm default CONFIGs into Kconfig and removed them
from default.mak, we made it harder to identify which CONFIGs are
selected by default in case users want to disable them.

Bring back the default entries into default.mak, but keep them
commented out. This way users can keep their workflows of editing
default.mak to remove build options without needing to search through
Kconfig.

Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230523180525.29994-3-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ff4367ce6ee8c54111a6792df7b6a6303ff1dd5e
      
https://github.com/qemu/qemu/commit/ff4367ce6ee8c54111a6792df7b6a6303ff1dd5e
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/Kconfig

  Log Message:
  -----------
  arm/Kconfig: Make TCG dependence explicit

Replace the 'default y if TCG' pattern with 'default y; depends on
TCG'.

That makes explict that there is a dependence on TCG and enabling
these CONFIGs via .mak files without TCG present will fail earlier.

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230523180525.29994-4-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c9bc788a4e05041bf09cf5edef4f36885c9faf8a
      
https://github.com/qemu/qemu/commit/c9bc788a4e05041bf09cf5edef4f36885c9faf8a
  Author: Enze Li <lienze@kylinos.cn>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M docs/conf.py
    M include/qemu/help-texts.h

  Log Message:
  -----------
  Update copyright dates to 2023

I noticed that in the latest version, the copyright string is still
2022, even though 2023 is halfway through.  This patch fixes that and
fixes the documentation along with it.

Signed-off-by: Enze Li <lienze@kylinos.cn>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230525064345.1152801-1-lienze@kylinos.cn
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 878fd6666939001efbef7fef350d2e11848dda4f
      
https://github.com/qemu/qemu/commit/878fd6666939001efbef7fef350d2e11848dda4f
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  hw/arm/sbsa-ref: add GIC node into DT

Let add GIC information into DeviceTree as part of SBSA-REF versioning.

Trusted Firmware will read it and provide to next firmware level.

Bumps platform version to 0.1 one so we can check is node is present.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b03d0d4f531a8b867e0aac1fab0b876903015680
      
https://github.com/qemu/qemu/commit/b03d0d4f531a8b867e0aac1fab0b876903015680
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M docs/system/arm/sbsa.rst

  Log Message:
  -----------
  docs: sbsa: correct graphics card name

We moved from VGA to Bochs to have PCIe card.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f1be1eafdc784ffdeb6496363f98dff2a7fa66fe
      
https://github.com/qemu/qemu/commit/f1be1eafdc784ffdeb6496363f98dff2a7fa66fe
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M configs/devices/aarch64-softmmu/default.mak
    M configs/devices/arm-softmmu/default.mak
    M docs/conf.py
    M docs/system/arm/sbsa.rst
    M hw/arm/Kconfig
    M hw/arm/fsl-imx6.c
    M hw/arm/sbsa-ref.c
    M hw/arm/smmu-common.c
    M hw/arm/smmu-internal.h
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/trace-events
    M hw/arm/xlnx-zynqmp.c
    M hw/dma/xilinx_axidma.c
    M include/hw/arm/fsl-imx6.h
    M include/hw/arm/smmu-common.h
    M include/hw/arm/smmuv3.h
    M include/qemu/help-texts.h
    M target/arm/Kconfig
    M target/arm/tcg/tlb_helper.c
    M tests/qtest/meson.build

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20230530' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * fsl-imx6: Add SNVS support for i.MX6 boards
 * smmuv3: Add support for stage 2 translations
 * hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop
 * hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
 * cleanups for recent Kconfig changes
 * target/arm: Explicitly select short-format FSR for M-profile
 * tests/qtest: Run arm-specific tests only if the required machine is available
 * hw/arm/sbsa-ref: add GIC node into DT
 * docs: sbsa: correct graphics card name
 * Update copyright dates to 2023

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# gpg: Signature made Tue 30 May 2023 06:22:30 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]

* tag 'pull-target-arm-20230530' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits)
  docs: sbsa: correct graphics card name
  hw/arm/sbsa-ref: add GIC node into DT
  Update copyright dates to 2023
  arm/Kconfig: Make TCG dependence explicit
  arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
  target/arm: Explain why we need to select ARM_V7M
  target/arm: Explicitly select short-format FSR for M-profile
  tests/qtest: Run arm-specific tests only if the required machine is available
  hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
  hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.
  hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2
  hw/arm/smmuv3: Add stage-2 support in iova notifier
  hw/arm/smmuv3: Add CMDs related to stage-2
  hw/arm/smmuv3: Add VMID to TLB tagging
  hw/arm/smmuv3: Make TLB lookup work for stage-2
  hw/arm/smmuv3: Parse STE config for stage-2
  hw/arm/smmuv3: Add page table walk for stage-2
  hw/arm/smmuv3: Refactor stage-1 PTW
  hw/arm/smmuv3: Update translation config to hold stage-2
  hw/arm/smmuv3: Add missing fields for IDR0
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/a4423a37859c...f1be1eafdc78