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[Qemu-commits] [qemu/qemu] 0ca52a: arm: move KVM breakpoints helpers
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 0ca52a: arm: move KVM breakpoints helpers |
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Date: |
Tue, 06 Jun 2023 08:52:31 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 0ca52a5fedeae3987ab2a84077d8ecb7d913aa37
https://github.com/qemu/qemu/commit/0ca52a5fedeae3987ab2a84077d8ecb7d913aa37
Author: Francesco Cagnin <fcagnin@quarkslab.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
A target/arm/hyp_gdbstub.c
M target/arm/internals.h
M target/arm/kvm64.c
M target/arm/meson.build
Log Message:
-----------
arm: move KVM breakpoints helpers
These helpers will be also used for HVF. Aside from reformatting a
couple of comments for 'checkpatch.pl' and updating meson to compile
'hyp_gdbstub.c', this is just code motion.
Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230601153107.81955-2-fcagnin@quarkslab.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ce799a04b2987e54a3f29b2139c9610ac8c467c9
https://github.com/qemu/qemu/commit/ce799a04b2987e54a3f29b2139c9610ac8c467c9
Author: Francesco Cagnin <fcagnin@quarkslab.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
hvf: handle access for more registers
Required for guest debugging.
Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
Message-id: 20230601153107.81955-3-fcagnin@quarkslab.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f41520402c3a917c378ad166c2c76feb64608b09
https://github.com/qemu/qemu/commit/f41520402c3a917c378ad166c2c76feb64608b09
Author: Francesco Cagnin <fcagnin@quarkslab.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M accel/hvf/hvf-accel-ops.c
M accel/hvf/hvf-all.c
M include/sysemu/hvf.h
M include/sysemu/hvf_int.h
M target/arm/hvf/hvf.c
M target/i386/hvf/hvf.c
Log Message:
-----------
hvf: add breakpoint handlers
Required for guest debugging. The code has been structured like the KVM
counterpart.
Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
Message-id: 20230601153107.81955-4-fcagnin@quarkslab.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eb2edc42b12683fdbe54003db7701f7ab6cda036
https://github.com/qemu/qemu/commit/eb2edc42b12683fdbe54003db7701f7ab6cda036
Author: Francesco Cagnin <fcagnin@quarkslab.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M accel/hvf/hvf-accel-ops.c
M accel/hvf/hvf-all.c
M include/sysemu/hvf.h
M include/sysemu/hvf_int.h
M target/arm/hvf/hvf.c
M target/arm/hvf_arm.h
M target/i386/hvf/hvf.c
Log Message:
-----------
hvf: add guest debugging handlers for Apple Silicon hosts
Guests can now be debugged through the gdbstub. Support is added for
single-stepping, software breakpoints, hardware breakpoints and
watchpoints. The code has been structured like the KVM counterpart.
While guest debugging is enabled, the guest can still read and write the
DBG*_EL1 registers but they don't have any effect.
Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
Message-id: 20230601153107.81955-5-fcagnin@quarkslab.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 32dbebcc7e375fef47834ac3951009468294db01
https://github.com/qemu/qemu/commit/32dbebcc7e375fef47834ac3951009468294db01
Author: Vikram Garhwal <vikram.garhwal@amd.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/net/can/meson.build
M hw/net/can/trace-events
A hw/net/can/xlnx-versal-canfd.c
A include/hw/net/xlnx-versal-canfd.h
Log Message:
-----------
hw/net/can: Introduce Xilinx Versal CANFD controller
The Xilinx Versal CANFD controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 042d6b02551eb40255a76131b2d60f996a51195c
https://github.com/qemu/qemu/commit/042d6b02551eb40255a76131b2d60f996a51195c
Author: Vikram Garhwal <vikram.garhwal@amd.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M docs/system/arm/xlnx-versal-virt.rst
M hw/arm/xlnx-versal-virt.c
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
xlnx-versal: Connect Xilinx VERSAL CANFD controllers
Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt
document with CANFD command line examples.
Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1d2a60299c6fe08076a02c1df83173b31890e9b2
https://github.com/qemu/qemu/commit/1d2a60299c6fe08076a02c1df83173b31890e9b2
Author: Vikram Garhwal <vikram.garhwal@amd.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Include canfd tests under Xilinx CAN
Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8976fd2b5e13a2623e0ab36df64dd3ed14624023
https://github.com/qemu/qemu/commit/8976fd2b5e13a2623e0ab36df64dd3ed14624023
Author: Vikram Garhwal <vikram.garhwal@amd.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/xlnx-canfd-test.c
Log Message:
-----------
tests/qtest: Introduce tests for Xilinx VERSAL CANFD controller
The QTests perform three tests on the Xilinx VERSAL CANFD controller:
Tests the CANFD controllers in loopback.
Tests the CANFD controllers in normal mode with CAN frame.
Tests the CANFD controllers in normal mode with CANFD frame.
Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8d9006aeca58e4635d58fdd620d52fe77c9eb00d
https://github.com/qemu/qemu/commit/8d9006aeca58e4635d58fdd620d52fe77c9eb00d
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/arm/Kconfig
A hw/arm/allwinner-r40.c
A hw/arm/bananapi_m2u.c
M hw/arm/meson.build
A include/hw/arm/allwinner-r40.h
Log Message:
-----------
hw: arm: Add bananapi M2-Ultra and allwinner-r40 support
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: dc2a070d125772fe30384596d4d4ce6d9950b004
https://github.com/qemu/qemu/commit/dc2a070d125772fe30384596d4d4ce6d9950b004
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/arm/allwinner-r40.c
A hw/misc/allwinner-r40-ccu.c
M hw/misc/meson.build
M include/hw/arm/allwinner-r40.h
A include/hw/misc/allwinner-r40-ccu.h
Log Message:
-----------
hw/arm/allwinner-r40: add Clock Control Unit
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d1e409c5831b2f48b285a4d00f84fbc6a3a927bb
https://github.com/qemu/qemu/commit/d1e409c5831b2f48b285a4d00f84fbc6a3a927bb
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/arm/allwinner-r40.c
M include/hw/arm/allwinner-r40.h
Log Message:
-----------
hw: allwinner-r40: Complete uart devices
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 44814e210acb589bfdab073b3bed3a6d9a306ca3
https://github.com/qemu/qemu/commit/44814e210acb589bfdab073b3bed3a6d9a306ca3
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/arm/allwinner-r40.c
M include/hw/arm/allwinner-r40.h
Log Message:
-----------
hw: arm: allwinner-r40: Add i2c0 device
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a95454309269d579d936f3c9c736b436910f74f8
https://github.com/qemu/qemu/commit/a95454309269d579d936f3c9c736b436910f74f8
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/arm/Kconfig
M hw/arm/bananapi_m2u.c
M hw/misc/Kconfig
R hw/misc/axp209.c
A hw/misc/axp2xx.c
M hw/misc/meson.build
M hw/misc/trace-events
Log Message:
-----------
hw/misc: Rename axp209 to axp22x and add support AXP221 PMU
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4a52ef61d901290da8ece2bf99546af1389ff7bb
https://github.com/qemu/qemu/commit/4a52ef61d901290da8ece2bf99546af1389ff7bb
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/arm/allwinner-r40.c
M hw/arm/bananapi_m2u.c
A hw/misc/allwinner-r40-dramc.c
M hw/misc/meson.build
M hw/misc/trace-events
M include/hw/arm/allwinner-r40.h
A include/hw/misc/allwinner-r40-dramc.h
Log Message:
-----------
hw/arm/allwinner-r40: add SDRAM controller device
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2c992b88ccfc28897e5523b847c3dc1a68be0e11
https://github.com/qemu/qemu/commit/2c992b88ccfc28897e5523b847c3dc1a68be0e11
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/arm/allwinner-r40.c
M hw/sd/allwinner-sdhost.c
M include/hw/sd/allwinner-sdhost.h
Log Message:
-----------
hw: sd: allwinner-sdhost: Add sun50i-a64 SoC support
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Also fix allwinner-r40's mmc controller type.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0de1b69315b1b386d96282fa0b407f568fc5ede9
https://github.com/qemu/qemu/commit/0de1b69315b1b386d96282fa0b407f568fc5ede9
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/arm/allwinner-r40.c
M hw/arm/bananapi_m2u.c
M include/hw/arm/allwinner-r40.h
Log Message:
-----------
hw: arm: allwinner-r40: Add emac and gmac support
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 05def917e113ef95ef712ffd96d614203f5e8397
https://github.com/qemu/qemu/commit/05def917e113ef95ef712ffd96d614203f5e8397
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M hw/arm/Kconfig
M hw/arm/allwinner-r40.c
M hw/misc/Kconfig
A hw/misc/allwinner-sramc.c
M hw/misc/meson.build
M hw/misc/trace-events
M include/hw/arm/allwinner-r40.h
A include/hw/misc/allwinner-sramc.h
Log Message:
-----------
hw: arm: allwinner-sramc: Add SRAM Controller support for R40
Only a few important registers are added, especially the SRAM_VER
register.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6c4f229a2e0d6f882bae389ce0c5bdaea712ce0f
https://github.com/qemu/qemu/commit/6c4f229a2e0d6f882bae389ce0c5bdaea712ce0f
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M tests/avocado/boot_linux_console.py
Log Message:
-----------
tests: avocado: boot_linux_console: Add test case for bpim2u
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8d7f954a7f05dc1e537378f14ce4da72c54dc43a
https://github.com/qemu/qemu/commit/8d7f954a7f05dc1e537378f14ce4da72c54dc43a
Author: qianfan Zhao <qianfanguijin@163.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
A docs/system/arm/bananapi_m2u.rst
M docs/system/target-arm.rst
Log Message:
-----------
docs: system: arm: Introduce bananapi_m2u
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
[PMM: Minor format fixes to correct sphinx errors]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0f08429c4689514f4752454b99d7bd4e23f1cb71
https://github.com/qemu/qemu/commit/0f08429c4689514f4752454b99d7bd4e23f1cb71
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Add commentary for CPUARMState.exclusive_high
Document the meaning of exclusive_high in a big-endian context,
and why we can't change it now.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cf1cbf50e8b8281428d1bcd02df955d2f59eb9e4
https://github.com/qemu/qemu/commit/cf1cbf50e8b8281428d1bcd02df955d2f59eb9e4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Add feature test for FEAT_LSE2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e452ca5af88fc49b3026c2de0f1e65fd18d1a656
https://github.com/qemu/qemu/commit/e452ca5af88fc49b3026c2de0f1e65fd18d1a656
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Introduce finalize_memop_{atom,pair}
Let finalize_memop_atom be the new basic function, with
finalize_memop and finalize_memop_pair testing FEAT_LSE2
to apply the appropriate atomicity.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c74cc082a6d3f8fde7778d26f600967582741967
https://github.com/qemu/qemu/commit/c74cc082a6d3f8fde7778d26f600967582741967
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_gen_qemu_ld_i128 for LDXP
While we don't require 16-byte atomicity here, using a single larger
load simplifies the code, and makes it a closer match to STXP.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d450bd0157be43d273116c3e3617883c8a0ac3d1
https://github.com/qemu/qemu/commit/d450bd0157be43d273116c3e3617883c8a0ac3d1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld}
While we don't require 16-byte atomicity here, using a single larger
operation simplifies the code. Introduce finalize_memop_asimd for this.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e6073d88cc1fb43b00be16f79d9d6b0f9d2276f5
https://github.com/qemu/qemu/commit/e6073d88cc1fb43b00be16f79d9d6b0f9d2276f5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G
This fixes a bug in that these two insns should have been using atomic
16-byte stores, since MTE is ARMv8.5 and LSE2 is mandatory from ARMv8.4.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e6dd5e782becfe6d51f3575c086f5bd7162421d0
https://github.com/qemu/qemu/commit/e6dd5e782becfe6d51f3575c086f5bd7162421d0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r
Round len_align to 16 instead of 8, handling an odd 8-byte as part
of the tail. Use MO_ATOM_NONE to indicate that all of these memory
ops have only byte atomicity.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5c13983e23de4095e2dfa8bc52333ef40ebe40db
https://github.com/qemu/qemu/commit/5c13983e23de4095e2dfa8bc52333ef40ebe40db
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Sink gen_mte_check1 into load/store_exclusive
No need to duplicate this check across multiple call sites.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6f47e7c18972802c428a5e03eb52a8f0a7bebe5c
https://github.com/qemu/qemu/commit/6f47e7c18972802c428a5e03eb52a8f0a7bebe5c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Load/store integer pair with one tcg operation
This is required for LSE2, where the pair must be treated atomically if
it does not cross a 16-byte boundary. But it simplifies the code to do
this always.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a75b66f617ed3e8b880df80291c0efad1e087675
https://github.com/qemu/qemu/commit/a75b66f617ed3e8b880df80291c0efad1e087675
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Hoist finalize_memop out of do_gpr_{ld, st}
We are going to need the complete memop beforehand,
so let's not compute it twice.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 03176bcd03621f44c5282f8c398c378ad12069ff
https://github.com/qemu/qemu/commit/03176bcd03621f44c5282f8c398c378ad12069ff
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Hoist finalize_memop out of do_fp_{ld, st}
We are going to need the complete memop beforehand,
so let's not compute it twice.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0a9091424d71bcb4638daee6260bbeed498310c4
https://github.com/qemu/qemu/commit/0a9091424d71bcb4638daee6260bbeed498310c4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Pass memop to gen_mte_check1*
Pass the completed memop to gen_mte_check1_mmuidx.
For the moment, do nothing more than extract the size.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3b97520c86e704b0533627c26b98173b71834bad
https://github.com/qemu/qemu/commit/3b97520c86e704b0533627c26b98173b71834bad
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Pass single_memop to gen_mte_checkN
Pass the individual memop to gen_mte_checkN.
For the moment, do nothing with it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 523da6b963455ce0a0e8d572d98d9cd91f952785
https://github.com/qemu/qemu/commit/523da6b963455ce0a0e8d572d98d9cd91f952785
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/internals.h
M target/arm/tcg/mte_helper.c
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Check alignment in helper_mte_check
Fixes a bug in that with SCTLR.A set, we should raise any
alignment fault before raising any MTE check fault.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 83f624d9bae9f75b7004484e5c8adcb64ac2c6b3
https://github.com/qemu/qemu/commit/83f624d9bae9f75b7004484e5c8adcb64ac2c6b3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/hflags.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Add SCTLR.nAA to TBFLAG_A64
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c1a1f80518d360b694b32d7a00cd91b79683d026
https://github.com/qemu/qemu/commit/c1a1f80518d360b694b32d7a00cd91b79683d026
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/helper-a64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Relax ordered/atomic alignment checks for LSE2
FEAT_LSE2 only requires that atomic operations not cross a
16-byte boundary. Ordered operations may be completely
unaligned if SCTLR.nAA is set.
Because this alignment check is so special, do it by hand.
Make sure not to keep TCG temps live across the branch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-17-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5096ec5b32f14906bbc16b0728066723f502fa71
https://github.com/qemu/qemu/commit/5096ec5b32f14906bbc16b0728066723f502fa71
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Move mte check for store-exclusive
Push the mte check behind the exclusive_addr check.
Document the several ways that we are still out of spec
with this implementation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b7559ff7ce54c66ffdcdf1e41906298371b99109
https://github.com/qemu/qemu/commit/b7559ff7ce54c66ffdcdf1e41906298371b99109
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M tests/tcg/aarch64/mte-7.c
Log Message:
-----------
tests/tcg/aarch64: Use stz2g in mte-7.c
We have many other instances of stg in the testsuite;
change these to provide an instance of stz2g.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6a6f4295748030e302a5768c5098a484d25a5b12
https://github.com/qemu/qemu/commit/6a6f4295748030e302a5768c5098a484d25a5b12
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M tests/tcg/multiarch/sigbus.c
Log Message:
-----------
tests/tcg/multiarch: Adjust sigbus.c
With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise
an alignment exception when the load crosses a 16-byte boundary.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 59b6b42cd3446862567637f3a7ab31d69c9bef51
https://github.com/qemu/qemu/commit/59b6b42cd3446862567637f3a7ab31d69c9bef51
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_LSE2 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cd4a47f907e6b4f91627fcdad5174ecb2570ad0e
https://github.com/qemu/qemu/commit/cd4a47f907e6b4f91627fcdad5174ecb2570ad0e
Author: Zhuojia Shen <chaosdefinition@hotmail.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: allow DC CVA[D]P in user mode emulation
DC CVAP and DC CVADP instructions can be executed in EL0 on Linux,
either directly when SCTLR_EL1.UCI == 1 or emulated by the kernel (see
user_cache_maint_handler() in arch/arm64/kernel/traps.c).
This patch enables execution of the two instructions in user mode
emulation.
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c81e4ab370e858550852b052f689a0a721b879d4
https://github.com/qemu/qemu/commit/c81e4ab370e858550852b052f689a0a721b879d4
Author: Zhuojia Shen <chaosdefinition@hotmail.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/dcpodp.c
A tests/tcg/aarch64/dcpop.c
Log Message:
-----------
tests/tcg/aarch64: add DC CVA[D]P tests
Test execution of DC CVAP and DC CVADP instructions under user mode
emulation.
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f9ac778898cb28307e0f91421aba34d43c34b679
https://github.com/qemu/qemu/commit/f9ac778898cb28307e0f91421aba34d43c34b679
Author: Zhuojia Shen <chaosdefinition@hotmail.com>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M target/arm/cpu.c
M target/arm/debug_helper.c
Log Message:
-----------
target/arm: trap DCC access in user mode emulation
Accessing EL0-accessible Debug Communication Channel (DCC) registers in
user mode emulation is currently enabled. However, it does not match
Linux behavior as Linux sets MDSCR_EL1.TDCC on startup to disable EL0
access to DCC (see __cpu_setup() in arch/arm64/mm/proc.S).
This patch fixes access_tdcc() to check MDSCR_EL1.TDCC for EL0 and sets
MDSCR_EL1.TDCC for user mode emulation to match Linux.
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
DS7PR12MB630905198DD8E69F6817544CAC4EA@DS7PR12MB6309.namprd12.prod.outlook.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: feea0234199469a53cd90644383cc45f04e5331f
https://github.com/qemu/qemu/commit/feea0234199469a53cd90644383cc45f04e5331f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-06 (Tue, 06 Jun 2023)
Changed paths:
M MAINTAINERS
M accel/hvf/hvf-accel-ops.c
M accel/hvf/hvf-all.c
A docs/system/arm/bananapi_m2u.rst
M docs/system/arm/emulation.rst
M docs/system/arm/xlnx-versal-virt.rst
M docs/system/target-arm.rst
M hw/arm/Kconfig
A hw/arm/allwinner-r40.c
A hw/arm/bananapi_m2u.c
M hw/arm/meson.build
M hw/arm/xlnx-versal-virt.c
M hw/arm/xlnx-versal.c
M hw/misc/Kconfig
A hw/misc/allwinner-r40-ccu.c
A hw/misc/allwinner-r40-dramc.c
A hw/misc/allwinner-sramc.c
R hw/misc/axp209.c
A hw/misc/axp2xx.c
M hw/misc/meson.build
M hw/misc/trace-events
M hw/net/can/meson.build
M hw/net/can/trace-events
A hw/net/can/xlnx-versal-canfd.c
M hw/sd/allwinner-sdhost.c
A include/hw/arm/allwinner-r40.h
M include/hw/arm/xlnx-versal.h
A include/hw/misc/allwinner-r40-ccu.h
A include/hw/misc/allwinner-r40-dramc.h
A include/hw/misc/allwinner-sramc.h
A include/hw/net/xlnx-versal-canfd.h
M include/hw/sd/allwinner-sdhost.h
M include/sysemu/hvf.h
M include/sysemu/hvf_int.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/hvf_arm.h
A target/arm/hyp_gdbstub.c
M target/arm/internals.h
M target/arm/kvm64.c
M target/arm/meson.build
M target/arm/tcg/cpu64.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/hflags.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate-sve.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
M target/i386/hvf/hvf.c
M tests/avocado/boot_linux_console.py
M tests/qtest/meson.build
A tests/qtest/xlnx-canfd-test.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/dcpodp.c
A tests/tcg/aarch64/dcpop.c
M tests/tcg/aarch64/mte-7.c
M tests/tcg/multiarch/sigbus.c
Log Message:
-----------
Merge tag 'pull-target-arm-20230606' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Support gdbstub (guest debug) in HVF
* xnlx-versal: Support CANFD controller
* bpim2u: New board model: Banana Pi BPI-M2 Ultra
* Emulate FEAT_LSE2
* allow DC CVA[D]P in user mode emulation
* trap DCC access in user mode emulation
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# gpg: Signature made Tue 06 Jun 2023 02:47:17 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20230606' of
https://git.linaro.org/people/pmaydell/qemu-arm: (42 commits)
target/arm: trap DCC access in user mode emulation
tests/tcg/aarch64: add DC CVA[D]P tests
target/arm: allow DC CVA[D]P in user mode emulation
target/arm: Enable FEAT_LSE2 for -cpu max
tests/tcg/multiarch: Adjust sigbus.c
tests/tcg/aarch64: Use stz2g in mte-7.c
target/arm: Move mte check for store-exclusive
target/arm: Relax ordered/atomic alignment checks for LSE2
target/arm: Add SCTLR.nAA to TBFLAG_A64
target/arm: Check alignment in helper_mte_check
target/arm: Pass single_memop to gen_mte_checkN
target/arm: Pass memop to gen_mte_check1*
target/arm: Hoist finalize_memop out of do_fp_{ld, st}
target/arm: Hoist finalize_memop out of do_gpr_{ld, st}
target/arm: Load/store integer pair with one tcg operation
target/arm: Sink gen_mte_check1 into load/store_exclusive
target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r
target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G
target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld}
target/arm: Use tcg_gen_qemu_ld_i128 for LDXP
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/7ce5a15fa633...feea02341994
- [Qemu-commits] [qemu/qemu] 0ca52a: arm: move KVM breakpoints helpers,
Richard Henderson <=