[Qemu-commits] [qemu/qemu] ab64da: tcg/tci: Adjust passing of MemOpIdx

[Richard Henderson]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ab64da79774060450046ce8c800eef000024dc8c
      
https://github.com/qemu/qemu/commit/ab64da79774060450046ce8c800eef000024dc8c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-07 (Wed, 07 Jun 2023)

  Changed paths:
    M tcg/tci.c
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  tcg/tci: Adjust passing of MemOpIdx

Since adding MO_ATOM_MASK, the maximum MemOpIdx requires 15 bits,
which overflows the 12 bit field allocated for TCI memory ops.
Expand the field to 16 bits for 2-operand memory ops, and place
the value in TCG_REG_TMP for 3-operand memory ops (same as we
already do for 4-operand memory ops).

Cures a debug assert for aarch64, with FEAT_LSE2 enabled.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0cabaef3ed13697e2da0ceb18b3da9e21d0b4d83
      
https://github.com/qemu/qemu/commit/0cabaef3ed13697e2da0ceb18b3da9e21d0b4d83
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-07 (Wed, 07 Jun 2023)

  Changed paths:
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  tcg/tci: Adjust call-clobbered regs for int128_t

We require either 2 or 4 registers to hold int128_t.
Failure to do so results in a register allocation assert.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 007cd176e590c77e91d1531ec5acbe86b15b0f00
      
https://github.com/qemu/qemu/commit/007cd176e590c77e91d1531ec5acbe86b15b0f00
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-07 (Wed, 07 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Only include tcg/oversized-guest.h if CONFIG_TCG

Fixes the build for --disable-tcg.

This header is only needed for cross-hosting.  Without CONFIG_TCG,
we know this is an AArch64 host, CONFIG_ATOMIC64 will be set, and
the TCG_OVERSIZED_GUEST block will never be compiled.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c81e2d5477c92b4a96c779bffbba3dddb23b91be
      
https://github.com/qemu/qemu/commit/c81e2d5477c92b4a96c779bffbba3dddb23b91be
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-07 (Wed, 07 Jun 2023)

  Changed paths:
    M .gitlab-ci.d/crossbuilds.yml

  Log Message:
  -----------
  gitlab: Add cross-arm64-kvm-only

We are not currently running a --disable-tcg test for arm64,
like we are for mips, ppc and s390x.  We have a job for the
native aarch64 runner, but it is not run by default and it
is not helpful for normal developer testing without access
to qemu's private runner.

Use --without-default-features to eliminate most tests.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dcc28ab603f30df5cc8be1f759b423e94ae7d10f
      
https://github.com/qemu/qemu/commit/dcc28ab603f30df5cc8be1f759b423e94ae7d10f
  Author: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
  Date:   2023-06-07 (Wed, 07 Jun 2023)

  Changed paths:
    M tests/qemu-iotests/194
    M tests/qemu-iotests/194.out

  Log Message:
  -----------
  iotests: fix 194: filter out racy postcopy-active event

The event is racy: it will not appear in the output if bitmap is
migrated during downtime period of migration and postcopy phase is not
started.

Fixes: ae00aa239847 "iotests: 194: test also migration of dirty bitmap"
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-Id: <20230607143606.1557395-1-vsementsov@yandex-team.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c102e29772186b9b29ccbb4aef0f5cedc46d9870
      
https://github.com/qemu/qemu/commit/c102e29772186b9b29ccbb4aef0f5cedc46d9870
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-07 (Wed, 07 Jun 2023)

  Changed paths:
    M .gitlab-ci.d/crossbuilds.yml
    M target/arm/ptw.c
    M tcg/tci.c
    M tcg/tci/tcg-target.c.inc
    M tests/qemu-iotests/194
    M tests/qemu-iotests/194.out

  Log Message:
  -----------
  Merge tag 'pull-ci-20230607' of https://gitlab.com/rth7680/qemu into staging

Fix TCI regressions vs Int128
Fix Arm build vs --disable-tcg
Fix iotest 194.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmSApKodHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/0mAf/f6+JI3tF+CxyWs+J
# 5LSDn8hosJefuy+jkhSM/aPIlX5gYvmoA7S/XNGrDG0+yNS5SriZKuyt9hB/gZ5D
# JFred7xuI0RmkEX3cnqFgsrtFmOYdx6G5tt4MU25uzKFyPgYg+6hsF0fotcFCPIp
# s2XIjEc7X1hk/xr4LRRxJeRrK+ZK48sN+K9HzITclKB3v11Dxv/a0OT2kdrPvlvb
# d/yNYewZrxM86vFmlIR/dT+M/qq7ULonlnH1HuWh8IaPO0owEyJPZPFw07C3ivUi
# uIplMcqk/2Um1R8zwUgaByINB3uVQXp1PyYsbjxvS34mdLwtYXF8b+/5Ma6tc3Tb
# sWkIXg==
# =NNK9
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 07 Jun 2023 08:39:22 AM PDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[ultimate]

* tag 'pull-ci-20230607' of https://gitlab.com/rth7680/qemu:
  iotests: fix 194: filter out racy postcopy-active event
  gitlab: Add cross-arm64-kvm-only
  target/arm: Only include tcg/oversized-guest.h if CONFIG_TCG
  tcg/tci: Adjust call-clobbered regs for int128_t
  tcg/tci: Adjust passing of MemOpIdx

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/f5e6786de481...c102e2977218