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[Qemu-commits] [qemu/qemu] 9c3640: docs: Fix trivial typos in vhost-user
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 9c3640: docs: Fix trivial typos in vhost-user.rst |
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Date: |
Sat, 10 Jun 2023 07:25:32 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 9c36407a4445de1f3e69d7a7a30e86dbb75a94e6
https://github.com/qemu/qemu/commit/9c36407a4445de1f3e69d7a7a30e86dbb75a94e6
Author: Milan Zamazal <mzamazal@redhat.com>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M docs/system/devices/vhost-user.rst
Log Message:
-----------
docs: Fix trivial typos in vhost-user.rst
Signed-off-by: Milan Zamazal <mzamazal@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 46e75a77a9f5a5d88e4c8bb6de37f1531aa7d8b0
https://github.com/qemu/qemu/commit/46e75a77a9f5a5d88e4c8bb6de37f1531aa7d8b0
Author: Michael Tokarev <mjt@tls.msk.ru>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M hw/virtio/virtio-qmp.c
Log Message:
-----------
hw/virtio/virtio-qmp.c: spelling: suppoted
Fixes: f3034ad71fcd0a6a58bc37830f182b307f089159
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Commit: 40b89515d026915a0593993712e322addac095b9
https://github.com/qemu/qemu/commit/40b89515d026915a0593993712e322addac095b9
Author: Michael Tokarev <mjt@tls.msk.ru>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M include/ui/clipboard.h
M qapi/cryptodev.json
M qga/qapi-schema.json
Log Message:
-----------
spelling: information
3 trivial fixes: 2 .json comments which goes to
executables, and 1 .h file comment.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 5fb9e8295531f957cf7ac20e89736c8963a25e04
https://github.com/qemu/qemu/commit/5fb9e8295531f957cf7ac20e89736c8963a25e04
Author: Mattias Nissler <mnissler@rivosinc.com>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M hw/remote/trace-events
Log Message:
-----------
hw/remote: Fix vfu_cfg trace offset format
The printed offset value is prefixed with 0x, but was actually printed
in decimal. To spare others the confusion, adjust the format specifier
to hexadecimal.
Signed-off-by: Mattias Nissler <mnissler@rivosinc.com>
Reviewed-by: Jagannathan Raman <jag.raman@oracle.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: fbdffb08dfe5db0ffed22619bad1772a675e11e2
https://github.com/qemu/qemu/commit/fbdffb08dfe5db0ffed22619bad1772a675e11e2
Author: Michael Tokarev <mjt@tls.msk.ru>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M block.c
Log Message:
-----------
block.c: add newline for "Detected format" warning
Add the forgotten trailing newline.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 890e37e27cd6b38a6e9bccf48c05700bab429b53
https://github.com/qemu/qemu/commit/890e37e27cd6b38a6e9bccf48c05700bab429b53
Author: Carlos Santos <casantos@redhat.com>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M pc-bios/keymaps/meson.build
Log Message:
-----------
meson: install keyboard maps only if necessary
They are required only for system emulation (i.e. have_system is true).
Signed-off-by: Carlos Santos <casantos@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: d8ca9712f58f05f5668c43678f132330f2636ac3
https://github.com/qemu/qemu/commit/d8ca9712f58f05f5668c43678f132330f2636ac3
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M target/m68k/fpu_helper.c
Log Message:
-----------
target/m68k/fpu_helper: Use FloatRelation enum to hold comparison result
Use the FloatRelation enum to hold the comparison result (missed
in commit 71bfd65c5f "softfloat: Name compare relation enum").
Inspired-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: bec552e2cdb1950e2cd5f1853c396ea91ec80253
https://github.com/qemu/qemu/commit/bec552e2cdb1950e2cd5f1853c396ea91ec80253
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M hw/core/cpu-common.c
Log Message:
-----------
hw/core/cpu: Simplify realize() using MACHINE_GET_CLASS() macro
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: a5c80ab847dada26137461e534f75bb9bcb85a89
https://github.com/qemu/qemu/commit/a5c80ab847dada26137461e534f75bb9bcb85a89
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M hw/i386/microvm.c
Log Message:
-----------
hw/i386/microvm: Simplify using object_dynamic_cast()
Use object_dynamic_cast() to determine if 'dev' is a TYPE_VIRTIO_MMIO.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 271233f21f66c10194a45c1bff1db61fe2694a22
https://github.com/qemu/qemu/commit/271233f21f66c10194a45c1bff1db61fe2694a22
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M hw/pci/pci.c
Log Message:
-----------
hw/pci/pci: Simplify pci_bar_address() using MACHINE_GET_CLASS() macro
Remove unnecessary intermediate variables.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 4c030dd00f617b432524f7f9627192cb9b328bcb
https://github.com/qemu/qemu/commit/4c030dd00f617b432524f7f9627192cb9b328bcb
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M hw/usb/hcd-ehci-pci.c
Log Message:
-----------
hw/usb/hcd-ehci-pci: Simplify using DEVICE_GET_CLASS() macro
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 725160fe56eb9f6b9b13214b9adf519c25b9d527
https://github.com/qemu/qemu/commit/725160fe56eb9f6b9b13214b9adf519c25b9d527
Author: Michael Tokarev <mjt@tls.msk.ru>
Date: 2023-06-09 (Fri, 09 Jun 2023)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: add comments for TARGET_NR_[gs]etgroups{,32}
There are 2 pairs of identical code (with different types)
for TARGET_NR_setgroups & TARGET_NR_setgroups32, and
for TARGET_NR_getgroups & TARGET_NR_getgroups32. Add
comments stating this fact, so that further modifications
are done in two places.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 8fbf89a9669520ac09b3ae0013ff3eb34f8cab23
https://github.com/qemu/qemu/commit/8fbf89a9669520ac09b3ae0013ff3eb34f8cab23
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: Return EINVAL for getgroups() with negative gidsetsize
Coverity doesn't like the way we might end up calling getgroups()
with a NULL grouplist pointer. This is fine for the special case
of gidsetsize == 0, but we will also do it if the guest passes
us a negative gidsetsize. (CID 1512465)
Explicitly fail the negative gidsetsize with EINVAL, as the kernel
does. This means we definitely only call the libc getgroups()
with valid parameters. It also brings the getgroups() code in
to line with the setgroups() code.
Possibly Coverity may still complain about getgroups(0, NULL), but
that would be a false positive.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: bdfca8a22f41e7ad47fd2dac71e4d1387e2c0d4e
https://github.com/qemu/qemu/commit/bdfca8a22f41e7ad47fd2dac71e4d1387e2c0d4e
Author: Anastasia Belova <abelova@astralinux.ru>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M ui/vnc-jobs.c
Log Message:
-----------
vnc: move assert in vnc_worker_thread_loop
job may be NULL if queue->exit is true. Check
it before dereference job.
Fixes: f31f9c1080 ("vnc: add magic cookie to VncState")
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: f101c25cd66dc4dea1135d2f1783a0786534923a
https://github.com/qemu/qemu/commit/f101c25cd66dc4dea1135d2f1783a0786534923a
Author: Andrew Jeffery <andrew@aj.id.au>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user: elfload: s/min_mmap_addr/mmap_min_addr/
As-is the error message can cause some confusion as the mentioned sysctl
attribute name is wrong:
https://www.kernel.org/doc/html/latest/admin-guide/sysctl/vm.html#mmap-min-addr
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: e928907105cfeb48b68cedce232bbd4784536707
https://github.com/qemu/qemu/commit/e928907105cfeb48b68cedce232bbd4784536707
Author: Andrew Jeffery <andrew@aj.id.au>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user: elfload: Specify -R is an option for qemu-user binaries
Given several different concepts are suggested for investigation, let's
not confuse e.g. ulimit's -R with what was actually intended.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: cce84fc9193e2566b4f7f9de5a13e7ed360d44d9
https://github.com/qemu/qemu/commit/cce84fc9193e2566b4f7f9de5a13e7ed360d44d9
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/pnv_xive2_regs.h
Log Message:
-----------
pnv/xive2: Add definition for TCTXT Config register
Add basic read/write support for the TCTXT Config register on P10. qemu
doesn't do anything with it yet, but it avoids logging a guest error
when skiboot configures the fused-core state:
qemu-system-ppc64 -machine powernv10 ... -d guest_errors
...
[ 0.131670000,5] XIVE: [ IC 00 ] Initializing XIVE block ID 0...
XIVE[0] - TCTXT: invalid read @140
XIVE[0] - TCTXT: invalid write @140
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-2-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 32af01f83a763ccbba39c1cbc424e1b724d233df
https://github.com/qemu/qemu/commit/32af01f83a763ccbba39c1cbc424e1b724d233df
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/pnv_xive2_regs.h
Log Message:
-----------
pnv/xive2: Add definition for the ESB cache configuration register
Add basic read/write support for the ESB cache configuration register
on P10. We don't model the ESB cache in qemu so reading/writing the
register won't do anything, but it avoids logging a guest error when
skiboot configures it:
qemu-system-ppc64 -machine powernv10 ... -d guest_errors
...
XIVE[0] - VC: invalid read @240
XIVE[0] - VC: invalid write @240
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-3-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: f0fc1c29a8163ce383d3bcb3aac0964747d2d8b1
https://github.com/qemu/qemu/commit/f0fc1c29a8163ce383d3bcb3aac0964747d2d8b1
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Allow writes to the Physical Thread Enable registers
Fix what was probably a silly mistake and allow to write the Physical
Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET
variant so it went unnoticed, but there's no reason to discard a write
to the full register, it is Read-Write.
Fixes: da71b7e3ed45 ("ppc/pnv: Add a XIVE2 controller to the POWER10 chip")
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-4-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: afca92071fc12402a8dee1ad68f66f22dd4b9872
https://github.com/qemu/qemu/commit/afca92071fc12402a8dee1ad68f66f22dd4b9872
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
pnv/xive2: Introduce macros to manipulate TIMA addresses
TIMA addresses are somewhat special and are split in several bit
fields with different meanings. This patch describes it and introduce
macros to more easily access the various fields.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-5-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6f2cbd133d44547fe71879271adaadf11f20965b
https://github.com/qemu/qemu/commit/6f2cbd133d44547fe71879271adaadf11f20965b
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/xive.c
Log Message:
-----------
pnv/xive2: Handle TIMA access through all ports
The Thread Interrupt Management Area (TIMA) can be accessed through 4
ports, targeted by the address. The base address of a TIMA
is using port 0 and the other ports are 0x80 apart. Using one port or
another can be useful to balance the load on the snoop buses. With
skiboot and linux, we currently use port 0, but as it tends to be
busy, another hypervisor is using port 1 for TIMA access.
The port address bits fall in between the special op indication
bits (the 2 MSBs) and the register offset bits (the 6 LSBs). They are
"don't care" for the hardware when processing a TIMA operation. This
patch filters out those port address bits so that a TIMA operation can
be triggered using any port.
It is also true for indirect access (through the IC BAR) and it's
actually nothing new, it was already the case on P9. Which helps here,
as the TIMA handling code is common between P9 (xive) and P10 (xive2).
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-6-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6c242e79b876b3570b8fd2f10f2a502467758e56
https://github.com/qemu/qemu/commit/6c242e79b876b3570b8fd2f10f2a502467758e56
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix nested-hv HEAI delivery
ppc hypervisors turn HEAI interrupts into program interrupts injected
into the guest that executed the illegal instruction, if the hypervisor
doesn't handle it some other way.
The nested-hv implementation failed to account for this HEAI->program
conversion. The virtual hypervisor wants to see the HEAI when running
a nested guest, so that interrupt type can be returned to its KVM
caller.
Fixes: 7cebc5db2eba6 ("target/ppc: Introduce a vhyp framework for nested HV
support")
Cc: balaton@eik.bme.hu
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230530132127.385001-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 34b4313070b5f5613fb8198806f57614826b0aac
https://github.com/qemu/qemu/commit/34b4313070b5f5613fb8198806f57614826b0aac
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Quiet down some error messages
When dumping the END and NVP tables ("info pic" from the HMP) on the
P10 model, we're likely to be flooded with error messages such as:
XIVE[0] - VST: invalid NVPT entry f33800 !?
The error is printed when finding an empty VSD in an indirect
table (thus END and NVP tables with skiboot), which is going to happen
when dumping the xive state. So let's tune down those messages. They
can be re-enabled easily with a macro if needed.
Those errors were already hidden on xive/P9, for the same reason.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230531150537.369350-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6494d2c1fd4ebc37b575130399a97a1fcfff1afc
https://github.com/qemu/qemu/commit/6494d2c1fd4ebc37b575130399a97a1fcfff1afc
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper_regs.c
M target/ppc/helper_regs.h
M target/ppc/machine.c
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
Log Message:
-----------
target/ppc: Fix PMU hflags calculation
Some of the PMU hflags bits can go out of synch, for example a store to
MMCR0 with PMCjCE=1 fails to update hflags correctly and results in
hflags mismatch:
qemu: fatal: TCG hflags mismatch (current:0x2408003d rebuilt:0x240a003d)
This can be reproduced by running perf on a recent machine.
Some of the fragility here is the duplication of PMU hflags calculations.
This change consolidates that in a single place to update pmu-related
hflags, to be called after a well defined state changes.
The post-load PMU update is pulled out of the MSR update because it does
not depend on the MSR value.
Fixes: 8b3d1c49a9f0 ("target/ppc: Add new PMC HFLAGS")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230530130447.372617-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 82ce3d5614b2ef3a00b92ecbff074d5476eff285
https://github.com/qemu/qemu/commit/82ce3d5614b2ef3a00b92ecbff074d5476eff285
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/power8-pmu.c
Log Message:
-----------
target/ppc: PMU do not clear MMCR0[FCECE] on performance monitor alert
FCECE does not get cleared according to the ISA v3.1B.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230530134313.387252-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2e9855555ebbbd4b22418b6bffce1f0f14234141
https://github.com/qemu/qemu/commit/2e9855555ebbbd4b22418b6bffce1f0f14234141
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix msgclrp interrupt type
msgclrp matches msgsndp and should clear PPC_INTERRUPT_DOORBELL.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230530130714.373215-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: fd7abfab662a2bd8bbf63ad52d4b58243cd9c409
https://github.com/qemu/qemu/commit/fd7abfab662a2bd8bbf63ad52d4b58243cd9c409
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Support directed privileged doorbell interrupt (SDOOR)
BookS msgsndp instruction to self or DPDES register can cause SDOOR
interrupts which crash QEMU with exception not implemented.
Linux does not use msgsndp in SMT1, and KVM only uses DPDES to cause
doorbells when emulating a SMT guest (which is not the default), so
this has gone unnoticed.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230530130526.372701-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c29b070418c79fa8e09d17e4b52f3ffddd393764
https://github.com/qemu/qemu/commit/c29b070418c79fa8e09d17e4b52f3ffddd393764
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/excp_helper.c
M target/ppc/power8-pmu.c
Log Message:
-----------
target/ppc: PMU implement PERFM interrupts
The PMU raises a performance monitor exception (causing an interrupt
when MSR[EE]=1) when MMCR0[PMAO] is set, and lowers it when clear.
Wire this up and implement the interrupt delivery for books. Linux perf
record can now collect PMI-driven samples.
fire_PMC_interrupt is renamed to perfm_alert, which matches a bit closer
to the new terminology used in the ISA and distinguishes the alert
condition (e.g., counter overflow) from the PERFM (or EBB) interrupts.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230530134313.387252-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 728fbfb57be5f4a3089a01f5c6ed72e0618b49ae
https://github.com/qemu/qemu/commit/728fbfb57be5f4a3089a01f5c6ed72e0618b49ae
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Remove single use function
The get_physical_address() function is a trivial wrapper of
get_physical_address_wtlb() that is only used once. Remove it and call
get_physical_address_wtlb() directly instead.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<302697d63d26caebefaeee1e45352145ebd0318a.1685448535.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 62860c5feaf4eb53acafd10b238374d3ef21229a
https://github.com/qemu/qemu/commit/62860c5feaf4eb53acafd10b238374d3ef21229a
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/cpu.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Remove "ext" parameter of ppcemb_tlb_check()
This is only used by one caller so simplify function by removing this
parameter and move the operation to the single place where it's used.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<b21f11ae20e8a8c2e8b5d943f2bff12b5356005a.1685448535.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 753441c8898e5de41e6051f9d1244e98849bb866
https://github.com/qemu/qemu/commit/753441c8898e5de41e6051f9d1244e98849bb866
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/cpu.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Move ppcemb_tlb_search() to mmu_common.c
This function is the only reason why ppcemb_tlb_check() is not static
to mmu_common.c but it also better fits in mmu_common.c so move it
there.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<b64fd712a773558dea9b84945c57785546c0ae2e.1685448535.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a1fa47fad12ea104b2d3f7f8b39f102bc16df539
https://github.com/qemu/qemu/commit/a1fa47fad12ea104b2d3f7f8b39f102bc16df539
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/cpu.h
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Remove some unneded line breaks
Make lines shorter and fix indentation in some functions prototypes.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<70952ba2d82141db1cf5cfcf4b227402be575874.1685448535.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: bb60364c202d0447fab78653b660a092b11378e4
https://github.com/qemu/qemu/commit/bb60364c202d0447fab78653b660a092b11378e4
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Simplify ppcemb_tlb_search()
No nead to store return value and break from loop when we can return
directly.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<d470118c3adcbd41b1a91779f6bb7cbdb2b0d346.1685448535.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2b23daa8ebaf184e89bd04eed21817620d600cc7
https://github.com/qemu/qemu/commit/2b23daa8ebaf184e89bd04eed21817620d600cc7
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Change ppcemb_tlb_check() to return bool
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<bacd1bcbe99c07930c29a9815915da9ac75f6920.1685448535.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a5436bc6ed4d385690546783f1799ea927f5ebd2
https://github.com/qemu/qemu/commit/a5436bc6ed4d385690546783f1799ea927f5ebd2
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Eliminate goto in mmubooke_check_tlb()
Move out checking PID registers into a separate function which makes
mmubooke_check_tlb() simpler and avoids using goto.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<bd84d5f38af0ba2983ccd5c07635db49267c828f.1685448535.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e025e8f5a8a7e32409bb4c7c509d752486113188
https://github.com/qemu/qemu/commit/e025e8f5a8a7e32409bb4c7c509d752486113188
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Fix lqarx to set cpu_reserve
lqarx does not set cpu_reserve, which causes stqcx. to never succeed.
Cc: qemu-stable@nongnu.org
Fixes: 94bf2658676 ("target/ppc: Use atomic load for LQ and LQARX")
Fixes: 57b38ffd0c6 ("target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ,
STQ")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230605025445.161932-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 392d328abe7534a6e852151740913e2cd50426bc
https://github.com/qemu/qemu/commit/392d328abe7534a6e852151740913e2cd50426bc
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Ensure stcx size matches larx
Differently-sized larx/stcx. pairs can succeed if the starting address
matches. Add a check to require the size of stcx. exactly match the larx
that established the reservation. Use the term "reserve_length" for this
state, which matches the terminology used in the ISA.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230605025445.161932-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2c901dca1863515bd71c3f351610f0698cb8f0b4
https://github.com/qemu/qemu/commit/2c901dca1863515bd71c3f351610f0698cb8f0b4
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Remove larx/stcx. memory barrier semantics
larx and stcx. are not defined to order any memory operations.
Remove the barriers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230605025445.161932-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 21ee07e7737a2dbba226a8d8192246e51855910d
https://github.com/qemu/qemu/commit/21ee07e7737a2dbba226a8d8192246e51855910d
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Rework store conditional to avoid branch
Rework store conditional to avoid a branch in the success case.
Change some of the variable names and layout while here so
gen_conditional_store more closely matches gen_stqcx_.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230605025445.161932-4-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 09d2db9f46e38e2da990df8ad914d735d764251a
https://github.com/qemu/qemu/commit/09d2db9f46e38e2da990df8ad914d735d764251a
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/ppc/ppc.c
Log Message:
-----------
target/ppc: Fix decrementer time underflow and infinite timer loop
It is possible to store a very large value to the decrementer that it
does not raise the decrementer exception so the timer is scheduled, but
the next time value wraps and is treated as in the past.
This can occur if (u64)-1 is stored on a zero-triggered exception, or
(u64)-1 is stored twice on an underflow-triggered exception, for
example.
If such a value is set in DECAR, it gets stored to the decrementer by
the timer function, which then immediately causes another timer, which
hangs QEMU.
Clamp the decrementer to the implemented width, and use that as the
value for the timer calculation, effectively preventing this overflow.
Reported-by: sdicaro@DDCI.com
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230530131214.373524-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 17dd1354c1d1aba9caf4af01e11aa7dbe128474f
https://github.com/qemu/qemu/commit/17dd1354c1d1aba9caf4af01e11aa7dbe128474f
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/ppc/ppc.c
Log Message:
-----------
target/ppc: Decrementer fix BookE semantics
The decrementer store function has logic that short-cuts the timer if a
very small value is stored (0, 1, or 2) and raises an interrupt
directly. There are two problem with this on BookE.
First is that BookE says a decrementer interrupt should not be raised
on a store of 0, only of a decrement from 1. Second is that raising
the irq directly will bypass the auto-reload logic in the booke decr
timer function, breaking autoreload when 1 or 2 is stored.
Fix this by removing that small-value special case. It makes this
tricky logic even more difficult to reason about, and it hardly matters
for performance.
Cc: sdicaro@DDCI.com
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230530131214.373524-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 8e67403a2cdde2dd43b43683f4478f3c8ed07cf4
https://github.com/qemu/qemu/commit/8e67403a2cdde2dd43b43683f4478f3c8ed07cf4
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M include/hw/ppc/openpic.h
Log Message:
-----------
hw/ppc/openpic: Do not open-code ROUND_UP() macro
While reviewing, the ROUND_UP() macro is easier to figure out.
Besides, the comment confirms we want to round up here.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230523061546.49031-1-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 12cae32fe1a18a4e89472e7f92b06a4eb1beb671
https://github.com/qemu/qemu/commit/12cae32fe1a18a4e89472e7f92b06a4eb1beb671
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M tests/avocado/tuxrun_baselines.py
Log Message:
-----------
tests/avocado/tuxrun_baselines: Fix ppc64 tests for binaries without slirp
The ppc64 tuxrun tests are currently failing if "slirp" has been
disabled in the binary since they are using "-netdev user" now.
We have to skip the test if this network backend is missing.
Fixes: 6ee3624236 ("improve code coverage for ppc64")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230606192802.666000-1-thuth@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 8a15ccee4d59b74be551dc7956d78bde2a52764a
https://github.com/qemu/qemu/commit/8a15ccee4d59b74be551dc7956d78bde2a52764a
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Implement gathering irq statistics
Count exceptions which can be queried with info irq monitor command.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230606220200.7EBCC74635C@zero.eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9ec08f3569be3bc8bfd4d9b8b0445b9136910661
https://github.com/qemu/qemu/commit/9ec08f3569be3bc8bfd4d9b8b0445b9136910661
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/ppc/Kconfig
Log Message:
-----------
hw/ppc/Kconfig: MAC_NEWWORLD should always select USB_OHCI_PCI
The PowerMacs have an OHCI controller soldered on the motherboard,
so this should always be enabled for the "mac99" machine.
This fixes the problem that QEMU aborts when the user tries to run
the "mac99" machine with a build that has been compiled with the
"--without-default-devices" configure switch.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230530102041.55527-1-thuth@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 374db3c82189cc0bab9b628b64b0087ee2a0e318
https://github.com/qemu/qemu/commit/374db3c82189cc0bab9b628b64b0087ee2a0e318
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M block.c
M docs/system/devices/vhost-user.rst
M hw/core/cpu-common.c
M hw/i386/microvm.c
M hw/pci/pci.c
M hw/remote/trace-events
M hw/usb/hcd-ehci-pci.c
M hw/virtio/virtio-qmp.c
M include/ui/clipboard.h
M linux-user/elfload.c
M linux-user/syscall.c
M pc-bios/keymaps/meson.build
M qapi/cryptodev.json
M qga/qapi-schema.json
M target/m68k/fpu_helper.c
M ui/vnc-jobs.c
Log Message:
-----------
Merge tag 'trivial-patches-20230610' of https://gitlab.com/mjt0k/qemu into
staging
trivial-patches-20230610
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# gpg: Signature made Fri 09 Jun 2023 11:43:41 PM PDT
# gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59
# gpg: issuer "mjt@tls.msk.ru"
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [unknown]
# gpg: aka "Michael Tokarev <mjt@debian.org>" [unknown]
# gpg: aka "Michael Tokarev <mjt@corpit.ru>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5
# Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59
* tag 'trivial-patches-20230610' of https://gitlab.com/mjt0k/qemu:
linux-user: elfload: Specify -R is an option for qemu-user binaries
linux-user: elfload: s/min_mmap_addr/mmap_min_addr/
vnc: move assert in vnc_worker_thread_loop
linux-user: Return EINVAL for getgroups() with negative gidsetsize
linux-user: add comments for TARGET_NR_[gs]etgroups{,32}
hw/usb/hcd-ehci-pci: Simplify using DEVICE_GET_CLASS() macro
hw/pci/pci: Simplify pci_bar_address() using MACHINE_GET_CLASS() macro
hw/i386/microvm: Simplify using object_dynamic_cast()
hw/core/cpu: Simplify realize() using MACHINE_GET_CLASS() macro
target/m68k/fpu_helper: Use FloatRelation enum to hold comparison result
meson: install keyboard maps only if necessary
block.c: add newline for "Detected format" warning
hw/remote: Fix vfu_cfg trace offset format
spelling: information
hw/virtio/virtio-qmp.c: spelling: suppoted
docs: Fix trivial typos in vhost-user.rst
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fdd0df5340a8ebc8de88078387ebc85c5af7b40f
https://github.com/qemu/qemu/commit/fdd0df5340a8ebc8de88078387ebc85c5af7b40f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-10 (Sat, 10 Jun 2023)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/pnv_xive2_regs.h
M hw/intc/xive.c
M hw/ppc/Kconfig
M hw/ppc/ppc.c
M include/hw/ppc/openpic.h
M include/hw/ppc/xive_regs.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/helper_regs.c
M target/ppc/helper_regs.h
M target/ppc/machine.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/translate.c
M tests/avocado/tuxrun_baselines.py
Log Message:
-----------
Merge tag 'pull-ppc-20230610' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2023-06-10:
This queue includes several assorted fixes for target/ppc emulation and
XIVE2. It also includes an openpic fix, an avocado fix for ppc64
binaries without slipr and a Kconfig change for MAC_NEWWORLD.
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# =EezE
# -----END PGP SIGNATURE-----
# gpg: Signature made Sat 10 Jun 2023 06:29:30 AM PDT
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20230610' of https://gitlab.com/danielhb/qemu: (29 commits)
hw/ppc/Kconfig: MAC_NEWWORLD should always select USB_OHCI_PCI
target/ppc: Implement gathering irq statistics
tests/avocado/tuxrun_baselines: Fix ppc64 tests for binaries without slirp
hw/ppc/openpic: Do not open-code ROUND_UP() macro
target/ppc: Decrementer fix BookE semantics
target/ppc: Fix decrementer time underflow and infinite timer loop
target/ppc: Rework store conditional to avoid branch
target/ppc: Remove larx/stcx. memory barrier semantics
target/ppc: Ensure stcx size matches larx
target/ppc: Fix lqarx to set cpu_reserve
target/ppc: Eliminate goto in mmubooke_check_tlb()
target/ppc: Change ppcemb_tlb_check() to return bool
target/ppc: Simplify ppcemb_tlb_search()
target/ppc: Remove some unneded line breaks
target/ppc: Move ppcemb_tlb_search() to mmu_common.c
target/ppc: Remove "ext" parameter of ppcemb_tlb_check()
target/ppc: Remove single use function
target/ppc: PMU implement PERFM interrupts
target/ppc: Support directed privileged doorbell interrupt (SDOOR)
target/ppc: Fix msgclrp interrupt type
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/2c256e77595c...fdd0df5340a8
- [Qemu-commits] [qemu/qemu] 9c3640: docs: Fix trivial typos in vhost-user.rst,
Richard Henderson <=