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[Qemu-commits] [qemu/qemu] bc0ec5: target/riscv/vector_helper.c: skip se
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] bc0ec5: target/riscv/vector_helper.c: skip set tail when v... |
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Date: |
Tue, 13 Jun 2023 21:39:53 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: bc0ec52eb258e55aa8a4a4ab89cb5c8ad49b30ee
https://github.com/qemu/qemu/commit/bc0ec52eb258e55aa8a4a4ab89cb5c8ad49b30ee
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: skip set tail when vta is zero
The function is a no-op if 'vta' is zero but we're still doing a lot of
stuff in this function regardless. vext_set_elems_1s() will ignore every
single time (since vta is zero) and we just wasted time.
Skip it altogether in this case. Aside from the code simplification
there's a noticeable emulation performance gain by doing it. For a
regular C binary that does a vectors operation like this:
=======
#define SZ 10000000
int main ()
{
int *a = malloc (SZ * sizeof (int));
int *b = malloc (SZ * sizeof (int));
int *c = malloc (SZ * sizeof (int));
for (int i = 0; i < SZ; i++)
c[i] = a[i] + b[i];
return c[SZ - 1];
}
=======
Emulating it with qemu-riscv64 and RVV takes ~0.3 sec:
$ time ~/work/qemu/build/qemu-riscv64 \
-cpu rv64,debug=false,vext_spec=v1.0,v=true,vlen=128 ./foo.out
real 0m0.303s
user 0m0.281s
sys 0m0.023s
With this skip we take ~0.275 sec:
$ time ~/work/qemu/build/qemu-riscv64 \
-cpu rv64,debug=false,vext_spec=v1.0,v=true,vlen=128 ./foo.out
real 0m0.274s
user 0m0.252s
sys 0m0.019s
This performance gain adds up fast when executing heavy benchmarks like
SPEC.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230427205708.246679-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6672e29d3bc8e1a855a9ee8209c7315b8bc94d19
https://github.com/qemu/qemu/commit/6672e29d3bc8e1a855a9ee8209c7315b8bc94d19
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Move zc* out of the experimental properties
Zc* extensions (version 1.0) are ratified.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230510030040.20528-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d63be18490e1931479ba6dc424de9c568d1419d8
https://github.com/qemu/qemu/commit/d63be18490e1931479ba6dc424de9c568d1419d8
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add riscv_cpu_validate_v()
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(), after we've already set some
extensions that are dependent on RVV. Let's put it in its own function
and do it earlier.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2238c9d196e90a991e83919802158f4232202039
https://github.com/qemu/qemu/commit/2238c9d196e90a991e83919802158f4232202039
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: remove set_vext_version()
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8c6eeb508a98b185fac71c4dad523763ab779a83
https://github.com/qemu/qemu/commit/8c6eeb508a98b185fac71c4dad523763ab779a83
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: remove set_priv_version()
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b9a2b98e172336e8ec464b3b63bf0dedba944502
https://github.com/qemu/qemu/commit/b9a2b98e172336e8ec464b3b63bf0dedba944502
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: add PRIV_VERSION_LATEST
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything at once when a new priv version is
available.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 61a33ea95a7efb7f9a211b1a812e9bb6e7525f1d
https://github.com/qemu/qemu/commit/61a33ea95a7efb7f9a211b1a812e9bb6e7525f1d
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Mask the implicitly enabled extensions in isa_string based on
priv version
Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their
super extensions can simplify the extension related check. However, they
may have higher priv version than their super extensions. So we should mask
them in the isa_string based on priv version to make them invisible to user
if the specified priv version is lower than their minimal priv version.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d33e39f995c377fee61281ddf44cd793e1a45625
https://github.com/qemu/qemu/commit/d33e39f995c377fee61281ddf44cd793e1a45625
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Update check for Zca/Zcf/Zcd
Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv
version is higher than the priv version of C/F/D. So if we use check
for them instead of check for C/F/D totally, it will trigger new
problem when we try to disable the extensions based on the configured
priv version.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bd30559568607324f467bff66d8644fc08cb4729
https://github.com/qemu/qemu/commit/bd30559568607324f467bff66d8644fc08cb4729
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
We're doing env->priv_spec validation and assignment at the start of
riscv_cpu_realize(), which is fine, but then we're doing a force disable
on extensions that aren't compatible with the priv version.
This second step is being done too early. The disabled extensions might be
re-enabled again in riscv_cpu_validate_set_extensions() by accident. A
better place to put this code is at the end of
riscv_cpu_validate_set_extensions() after all the validations are
completed.
Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the
extesions after the validation is done. While we're at it, create a
riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related
validation to unclog riscv_cpu_realize a bit.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f5664064cc808dc5057627fbb0e5d68a394f2fc1
https://github.com/qemu/qemu/commit/f5664064cc808dc5057627fbb0e5d68a394f2fc1
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e2fa85f42f0bddcfcb2249b1757a9e1a209ae4e3
https://github.com/qemu/qemu/commit/e2fa85f42f0bddcfcb2249b1757a9e1a209ae4e3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: validate extensions before riscv_timer_init()
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7f0bdfb5bfc2b6f1199f8b09e3b6dc9015b7b9c3
https://github.com/qemu/qemu/commit/7f0bdfb5bfc2b6f1199f8b09e3b6dc9015b7b9c3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every time, and every
other CPU should always account for them. CPUs such as sifive_e need to
disable settings that aren't enabled simply because the parent class
happens to be enabling it.
Moving all configurations from the parent class to each CPU will
centralize the config of each CPU into its own init(), which is clearer
than having to account to whatever happens to be set in the parent
device. These settings are also being set in register_cpu_props() when
no 'misa_ext' is set, so for these CPUs we don't need changes. Named
CPUs will receive all cfgs that the parent were setting into their
init().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: faf3b5d86ff3b0349ded42f8ef3240d1960b6a1a
https://github.com/qemu/qemu/commit/faf3b5d86ff3b0349ded42f8ef3240d1960b6a1a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: rework write_misa()
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Our validation is done with riscv_cpu_validate_set_extensions(), but we
need a small tweak first. When enabling RVG we're doing:
env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
env->misa_ext_mask = env->misa_ext;
This works fine for realize() time but this can potentially overwrite
env->misa_ext_mask if we reutilize the function for write_misa().
Instead of doing misa_ext_mask = misa_ext, sum up the RVG extensions in
misa_ext_mask as well. This won't change realize() time behavior
(misa_ext_mask will be == misa_ext) and will ensure that write_misa()
won't change misa_ext_mask by accident.
After that, rewrite write_misa() to work as follows:
- mask the write using misa_ext_mask to avoid enabling unsupported
extensions;
- suppress RVC if the next insn isn't aligned;
- disable RVG if any of RVG dependencies are being disabled by the user;
- assign env->misa_ext and run riscv_cpu_validate_set_extensions(). On
error, rollback env->misa_ext to its original value, logging a
GUEST_ERROR to inform the user about the failed write;
- handle RVF and MSTATUS_FS and continue as usual.
Let's keep write_misa() as experimental for now until this logic gains
enough mileage.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230517135714.211809-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dc7b599332c26065cd9ff1f2f2cf3ed580ca3dfd
https://github.com/qemu/qemu/commit/dc7b599332c26065cd9ff1f2f2cf3ed580ca3dfd
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/pmp.c
M target/riscv/pmp.h
Log Message:
-----------
target/riscv: Update pmp_get_tlb_size()
PMP entries before (including) the matched PMP entry may only cover partial
of the TLB page, and this may split the page into regions with different
permissions. Such as for PMP0 (0x80000008~0x8000000F, R) and PMP1 (0x80000000~
0x80000FFF, RWX), write access to 0x80000000 will match PMP1. However we cannot
cache the translation result in the TLB since this will make the write access
to 0x80000008 bypass the check of PMP0. So we should check all of them instead
of the matched PMP entry in pmp_get_tlb_size() and set the tlb_size to 1 in
this case.
Set tlb_size to TARGET_PAGE_SIZE if PMP is not support or there is no PMP rules.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bfc7ee1224152782e6624fcc859ffa52b73c1531
https://github.com/qemu/qemu/commit/bfc7ee1224152782e6624fcc859ffa52b73c1531
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
pmp_get_tlb_size can be separated from get_physical_address_pmp and is only
needed when ret == TRANSLATE_SUCCESS.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 093ce837e1facb4168fbe24974ee92220cdd1907
https://github.com/qemu/qemu/commit/093ce837e1facb4168fbe24974ee92220cdd1907
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Make the short cut really work in pmp_hart_has_privs
Return the result directly for short cut, since We needn't do the
following check on the PMP entries if there is no PMP rules.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e9c39713ea09faa74f502e32d71d52c1c2e8ccf1
https://github.com/qemu/qemu/commit/e9c39713ea09faa74f502e32d71d52c1c2e8ccf1
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/pmp.c
M target/riscv/pmp.h
Log Message:
-----------
target/riscv: Change the return type of pmp_hart_has_privs() to bool
We no longer need the pmp_index for matched PMP entry now.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b84ffd6e74b5e4e7ddbb492bc9c8d798c8261703
https://github.com/qemu/qemu/commit/b84ffd6e74b5e4e7ddbb492bc9c8d798c8261703
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
RLB/MML/MMWP bits in mseccfg CSR are introduced by Smepmp extension.
So they can only be writable and set to 1s when cfg.epmp is true.
Then we also need't check on epmp in pmp_hart_has_privs_default().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 97ec5aef082d8b40a0a37d4d6274ffe165ef27b7
https://github.com/qemu/qemu/commit/97ec5aef082d8b40a0a37d4d6274ffe165ef27b7
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
The addr and size parameters in pmp_hart_has_privs_default() are unused.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 37e79058031b0490734f724edf4e1691f6b3601e
https://github.com/qemu/qemu/commit/37e79058031b0490734f724edf4e1691f6b3601e
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Flush TLB when MMWP or MML bits are changed
MMWP and MML bits may affect the allowed privs of PMP entries and the
default privs, both of which may change the allowed privs of exsited
TLB entries. So we need flush TLB when they are changed.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2b3e127856b8a0a6a3a6dfa815f3165810436483
https://github.com/qemu/qemu/commit/2b3e127856b8a0a6a3a6dfa815f3165810436483
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Update the next rule addr in pmpaddr_csr_write()
Currently only the rule addr of the same index of pmpaddr is updated
when pmpaddr CSR is modified. However, the rule addr of next PMP entry
may also be affected if its A field is PMP_AMATCH_TOR. So we should
also update it in this case.
Write to pmpaddr CSR will not affect the rule nums, So we needn't update
call pmp_update_rule_nums() in pmpaddr_csr_write().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7c4c31f6d977c54751ca33ac5d77583faf20872d
https://github.com/qemu/qemu/commit/7c4c31f6d977c54751ca33ac5d77583faf20872d
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Flush TLB when pmpaddr is updated
TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230517091519.34439-10-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e924074f1367f6b808aedd3359fb00f261adb405
https://github.com/qemu/qemu/commit/e924074f1367f6b808aedd3359fb00f261adb405
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
TLB needn't be flushed when pmpcfg/pmpaddr don't changes.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230517091519.34439-11-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1b63f2fee68e28566c218bdf34988f8c5978b1e4
https://github.com/qemu/qemu/commit/1b63f2fee68e28566c218bdf34988f8c5978b1e4
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to
update rule nums only once for each pmpcfg_csr_write. Then remove
pmp_update_rule() since it become unused.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-12-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 89fbbaddfb33556f3f669d40f917c65e75ea6768
https://github.com/qemu/qemu/commit/89fbbaddfb33556f3f669d40f917c65e75ea6768
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Deny access if access is partially inside the PMP entry
Access will fail if access is partially inside the PMP entry.
However,only setting ret = false doesn't really mean pmp violation
since pmp_hart_has_privs_default() may return true at the end of
pmp_hart_has_privs().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-13-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9b29697fefa59431984aed9118e6fc062da0ee10
https://github.com/qemu/qemu/commit/9b29697fefa59431984aed9118e6fc062da0ee10
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/riscv/opentitan.c
Log Message:
-----------
hw/riscv/opentitan: Rename machine_[class]_init() functions
Follow QOM style which declares FOO_init() as instance
initializer and FOO_class_init() as class initializer:
rename the OpenTitan machine class/instance init()
accordingly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e0782b11bd7ef0c8e5cb9b5e83c32736a143deee
https://github.com/qemu/qemu/commit/e0782b11bd7ef0c8e5cb9b5e83c32736a143deee
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/riscv/opentitan.c
Log Message:
-----------
hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination. This
is in preparation of adding the OpenTitan machine type to
this array in a pair of commits.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 264495f9486ac17ea0275b0de1510b5de32d142b
https://github.com/qemu/qemu/commit/264495f9486ac17ea0275b0de1510b5de32d142b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/riscv/opentitan.c
M include/hw/riscv/opentitan.h
Log Message:
-----------
hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
QOM type names are usually defined as TYPE_FOO.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-4-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8696b74a6fed86a9d2bd7e947d0490c2459a8aa6
https://github.com/qemu/qemu/commit/8696b74a6fed86a9d2bd7e947d0490c2459a8aa6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/riscv/opentitan.c
M include/hw/riscv/opentitan.h
Log Message:
-----------
hw/riscv/opentitan: Explicit machine type definition
Expand the DEFINE_MACHINE() macro, converting the class_init()
handler.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-5-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a828ba9d46972e32c135f386dd08c02aa7eb8f1d
https://github.com/qemu/qemu/commit/a828ba9d46972e32c135f386dd08c02aa7eb8f1d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/riscv/opentitan.c
M include/hw/riscv/opentitan.h
Log Message:
-----------
hw/riscv/opentitan: Correct OpenTitanState parent type/size
OpenTitanState is the 'machine' (or 'board') state: it isn't
a SysBus device, but inherits from the MachineState type.
Correct the instance size.
Doing so we avoid leaking an OpenTitanState pointer in
opentitan_machine_init().
Fixes: fe0fe4735e ("riscv: Initial commit of OpenTitan machine")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-6-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b9cedbf19cb4be04908a3a623f0f237875483499
https://github.com/qemu/qemu/commit/b9cedbf19cb4be04908a3a623f0f237875483499
Author: Yin Wang <yin.wang@intel.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/riscv/numa.c
Log Message:
-----------
hw/riscv: qemu crash when NUMA nodes exceed available CPUs
Command "qemu-system-riscv64 -machine virt
-m 2G -smp 1 -numa node,mem=1G -numa node,mem=1G"
would trigger this problem.Backtrace with:
#0 0x0000555555b5b1a4 in riscv_numa_get_default_cpu_node_id at
../hw/riscv/numa.c:211
#1 0x00005555558ce510 in machine_numa_finish_cpu_init at
../hw/core/machine.c:1230
#2 0x00005555558ce9d3 in machine_run_board_init at ../hw/core/machine.c:1346
#3 0x0000555555aaedc3 in qemu_init_board at ../softmmu/vl.c:2513
#4 0x0000555555aaf064 in qmp_x_exit_preconfig at ../softmmu/vl.c:2609
#5 0x0000555555ab1916 in qemu_init at ../softmmu/vl.c:3617
#6 0x000055555585463b in main at ../softmmu/main.c:47
This commit fixes the issue by adding parameter checks.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Yin Wang <yin.wang@intel.com>
Message-Id: <20230519023758.1759434-1-yin.wang@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7b945bdc0b10eda16dbeafe6a4dc1480176db38e
https://github.com/qemu/qemu/commit/7b945bdc0b10eda16dbeafe6a4dc1480176db38e
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix pointer mask transformation for vector address
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230524015933.17349-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 30a0d77622d105908e7d45cf34c73f781263ede5
https://github.com/qemu/qemu/commit/30a0d77622d105908e7d45cf34c73f781263ede5
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Update cur_pmmask/base when xl changes
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230524015933.17349-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9514fc72d0b92a973297fea0c82d64232a64d127
https://github.com/qemu/qemu/commit/9514fc72d0b92a973297fea0c82d64232a64d127
Author: Mayuresh Chitale <mchitale@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: smstateen check for fcsr
Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec
and check for it when accessing the fcsr register and its fields.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230518175058.2772506-2-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e0b343b5fa493f273e0e6d98d632b4360ebd6def
https://github.com/qemu/qemu/commit/e0b343b5fa493f273e0e6d98d632b4360ebd6def
Author: Mayuresh Chitale <mchitale@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/insn_trans/trans_rvf.c.inc
Log Message:
-----------
target/riscv: Reuse tb->flags.FS
When misa.F is 0 tb->flags.FS field is unused and can be used to save
the current state of smstateen0.FCSR check which is needed by the
floating point translation routines.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230518175058.2772506-3-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3594e3e584d2863e3929a23dd784688942ba167f
https://github.com/qemu/qemu/commit/3594e3e584d2863e3929a23dd784688942ba167f
Author: Mayuresh Chitale <mchitale@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: smstateen knobs
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230518175058.2772506-4-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d02eb5bcdeb3d3890404c1cc688cbcfcbd3ca65b
https://github.com/qemu/qemu/commit/d02eb5bcdeb3d3890404c1cc688cbcfcbd3ca65b
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M include/disas/dis-asm.h
Log Message:
-----------
disas: Change type of disassemble_info.target_info to pointer
Use pointer to pass more information of target to disasembler,
such as pass cpu.cfg related information in following commits.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b902ff2946adcc72d65604321ae3ca2fb41ae644
https://github.com/qemu/qemu/commit/b902ff2946adcc72d65604321ae3ca2fb41ae644
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.h
A target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h
Split RISCVCPUConfig declarations to prepare for passing it to disas.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230523093539.203909-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 454c2201005b5f47a76116ab529c923e194ec615
https://github.com/qemu/qemu/commit/454c2201005b5f47a76116ab529c923e194ec615
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M disas/riscv.c
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2a2b221b65f5a4bcbbb9b508cdb76ff527e48aa6
https://github.com/qemu/qemu/commit/2a2b221b65f5a4bcbbb9b508cdb76ff527e48aa6
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv.c: Support disas for Zcm* extensions
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c54dab4c85f2ce67c6566f3b01a1e09ebfab8c57
https://github.com/qemu/qemu/commit/c54dab4c85f2ce67c6566f3b01a1e09ebfab8c57
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv.c: Support disas for Z*inx extensions
Support disas for Z*inx instructions only when Zfinx extension is supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8deb4756a9d9ed271d05b2eeffa0e0e1483669f3
https://github.com/qemu/qemu/commit/8deb4756a9d9ed271d05b2eeffa0e0e1483669f3
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector
instructions are the same op index as their own. And they have no
functional decomp_data. So they have no functional difference from just
leaving them as zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 98624d137321c5cda021437c0f02cdf40ee7f752
https://github.com/qemu/qemu/commit/98624d137321c5cda021437c0f02cdf40ee7f752
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv.c: Fix lines with over 80 characters
Fix lines with over 80 characters.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3bd87176eeb3dee494ccaac56d9f77160c87bb9f
https://github.com/qemu/qemu/commit/3bd87176eeb3dee494ccaac56d9f77160c87bb9f
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv.c: Remove redundant parentheses
Remove redundant parenthese and fix multi-line comments.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bfc4f9e351e77c69fe21315815bc5db8ef7c22df
https://github.com/qemu/qemu/commit/bfc4f9e351e77c69fe21315815bc5db8ef7c22df
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Fix target address to update badaddr
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it into badaddr
and restore cpu_pc to current pc if exception is triggered.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8ef23a329accd36394ffbddf87cc18ef0209dd6b
https://github.com/qemu/qemu/commit/8ef23a329accd36394ffbddf87cc18ef0209dd6b
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Introduce cur_insn_len into DisasContext
Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1df8497b9d21a15a2dac1ecb49c9f07096e31ce2
https://github.com/qemu/qemu/commit/1df8497b9d21a15a2dac1ecb49c9f07096e31ce2
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Change gen_goto_tb to work on displacements
Reduce reliance on absolute value to prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 022c7550d994496d38c035e2290f9f8979065bad
https://github.com/qemu/qemu/commit/022c7550d994496d38c035e2290f9f8979065bad
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvzawrs.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Change gen_set_pc_imm to gen_update_pc
Reduce reliance on absolute values(by passing pc difference) to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 227fb82f99ac2d147c15342b2c83c7f6c28f20d2
https://github.com/qemu/qemu/commit/227fb82f99ac2d147c15342b2c83c7f6c28f20d2
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Use true diff for gen_pc_plus_diff
Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 356c13f94dbff3f32e9d3615f6caa35a2a324d8d
https://github.com/qemu/qemu/commit/356c13f94dbff3f32e9d3615f6caa35a2a324d8d
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Enable PC-relative translation
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Use gen_pc_plus_diff to get the pc-relative address.
Enable CF_PCREL in System mode.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 90b0aecaf9148cc3a78abee7deb824ca6cf13ad5
https://github.com/qemu/qemu/commit/90b0aecaf9148cc3a78abee7deb824ca6cf13ad5
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Remove pc_succ_insn from DisasContext
pc_succ_insn is no longer useful after the introduce of cur_insn_len
and all pc related value use diff value instead of absolute value.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4263e270a240cee6e17ae76a752ab2a76493a779
https://github.com/qemu/qemu/commit/4263e270a240cee6e17ae76a752ab2a76493a779
Author: Sunil V L <sunilvl@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
Currently, virt machine supports two pflash instances each with
32MB size. However, the first pflash is always assumed to
contain M-mode firmware and reset vector is set to this if
enabled. Hence, for S-mode payloads like EDK2, only one pflash
instance is available for use. This means both code and NV variables
of EDK2 will need to use the same pflash.
The OS distros keep the EDK2 FW code as readonly. When non-volatile
variables also need to share the same pflash, it is not possible
to keep it as readonly since variables need write access.
To resolve this issue, the code and NV variables need to be separated.
But in that case we need an extra flash. Hence, modify the convention
for non-KVM guests such that, pflash0 will contain the M-mode FW
only when "-bios none" option is used. Otherwise, pflash0 will contain
the S-mode payload FW. This enables both pflash instances available
for EDK2 use.
When KVM is enabled, pflash0 is always assumed to contain the
S-mode payload firmware only.
Example usage:
1) pflash0 containing M-mode FW
qemu-system-riscv64 -bios none -pflash <mmode_fw> -machine virt
or
qemu-system-riscv64 -bios none \
-drive file=<mmode_fw>,if=pflash,format=raw,unit=0 -machine virt
2) pflash0 containing S-mode payload like EDK2
qemu-system-riscv64 -pflash <smode_fw_code> -pflash <smode_vars> -machine virt
or
qemu-system-riscv64 -bios <opensbi_fw> \
-pflash <smode_fw_code> \
-pflash <smode_vars> \
-machine virt
or
qemu-system-riscv64 -bios <opensbi_fw> \
-drive file=<smode_fw_code>,if=pflash,format=raw,unit=0,readonly=on \
-drive file=<smode_fw_vars>,if=pflash,format=raw,unit=1 \
-machine virt
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230601045910.18646-2-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 13bdfb8b5487ad5f68529a53bff09e8a57482206
https://github.com/qemu/qemu/commit/13bdfb8b5487ad5f68529a53bff09e8a57482206
Author: Sunil V L <sunilvl@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
riscv/virt: Support using pflash via -blockdev option
Currently, pflash devices can be configured only via -pflash
or -drive options. This is the legacy way and the
better way is to use -blockdev as in other architectures.
libvirt also has moved to use -blockdev method.
To support -blockdev option, pflash devices need to be
created in instance_init itself. So, update the code to
move the virt_flash_create() to instance_init. Also, use
standard interfaces to detect whether pflash0 is
configured or not.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reported-by: Andrea Bolognani <abologna@redhat.com>
Tested-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230601045910.18646-3-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e158a6520a690b98242b9ecb53d25aa639641547
https://github.com/qemu/qemu/commit/e158a6520a690b98242b9ecb53d25aa639641547
Author: Sunil V L <sunilvl@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M docs/system/riscv/virt.rst
Log Message:
-----------
docs/system: riscv: Add pflash usage details
pflash devices can be used in virt machine for different
purposes like for ROM code or S-mode FW payload. Add a
section in the documentation on how to use pflash devices
for different purposes.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230601045910.18646-4-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b84694defbcc675a42bc35c4eb28cac590a5414b
https://github.com/qemu/qemu/commit/b84694defbcc675a42bc35c4eb28cac590a5414b
Author: Ivan Klokov <ivan.klokov@syntacore.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M accel/tcg/cpu-exec.c
M include/hw/core/cpu.h
M include/qemu/log.h
M util/log.c
Log Message:
-----------
util/log: Add vector registers to log
Added QEMU option 'vpu' to log vector extension registers such as gpr\fpu.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230410124451.15929-2-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b83e4f1db44e2b58227bd5b0a2e3d8fd755b2881
https://github.com/qemu/qemu/commit/b83e4f1db44e2b58227bd5b0a2e3d8fd755b2881
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Fix initialized value for cur_pmmask
We initialize cur_pmmask as -1(UINT32_MAX/UINT64_MAX) and regard it
as if pointer mask is disabled in current implementation. However,
the addresses for vector load/store will be adjusted to zero in this
case and -1(UINT32_MAX/UINT64_MAX) is valid value for pmmask when
pointer mask is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230610094651.43786-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fba59e0f46a0a17a5aa0e57439a11b7048d3f2c6
https://github.com/qemu/qemu/commit/fba59e0f46a0a17a5aa0e57439a11b7048d3f2c6
Author: Xiao Wang <xiao.w.wang@intel.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: clean up reference of MTYPE
There's no code using MTYPE, which was a concept used in older vector
implementation.
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230608053517.4102648-1-xiao.w.wang@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 949b6bcb27295eb04350afac32a45b698fc50104
https://github.com/qemu/qemu/commit/949b6bcb27295eb04350afac32a45b698fc50104
Author: Xiao Wang <xiao.w.wang@intel.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: Remove the check for extra tail elements
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added an extra check for LMUL fragmentation,
intended for setting the "rest tail elements" in the last register for a
segment load insn.
Actually, the max_elements derived in vext_ld*() won't be a fraction of
vector register size, since the lmul encoded in desc is emul, which has
already been adjusted to 1 for LMUL fragmentation case by vext_get_emul()
in trans_rvv.c.inc, for ld_stride(), ld_us(), ld_index() and ldff().
Besides, vext_get_emul() has also taken EEW/SEW into consideration, so no
need to call vext_get_total_elems() which would base on the emul to derive
another emul, the second emul would be incorrect when esz differs from sew.
Thus this patch removes the check for extra tail elements.
Fixes: 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector load /
store instructions")
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230607091646.4049428-1-xiao.w.wang@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a574b27af4fe340684ca9f20560a1b01905e4364
https://github.com/qemu/qemu/commit/a574b27af4fe340684ca9f20560a1b01905e4364
Author: Himanshu Chauhan <hchauhan@ventanamicro.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Smepmp: Return error when access permission not allowed in PMP
On an address match, skip checking for default permissions and return error
based on access defined in PMP configuration.
v3 Changes:
o Removed explicit return of boolean value from comparision
of priv/allowed_priv
v2 Changes:
o Removed goto to return in place when address matches
o Call pmp_hart_has_privs_default at the end of the loop
Fixes: 90b1fafce06 ("target/riscv: Smepmp: Skip applying default rules when
address matches")
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230605164548.715336-1-hchauhan@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7f750efcaa86dad4d0b748f27b82c2c066b5435b
https://github.com/qemu/qemu/commit/7f750efcaa86dad4d0b748f27b82c2c066b5435b
Author: Andreas Schwab <schwab@suse.de>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M bsd-user/main.c
M linux-user/main.c
Log Message:
-----------
linux-user, bsd-user: Preserve incoming order of environment variables in the
target
Do not reverse the order of environment variables in the target environ
array relative to the incoming environ order. Some testsuites depend on a
specific order, even though it is not defined by any standard.
Signed-off-by: Andreas Schwab <schwab@suse.de>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <mvmlejfsivd.fsf@suse.de>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f975033d56dbf945ca7a4247c301c217fa4972f8
https://github.com/qemu/qemu/commit/f975033d56dbf945ca7a4247c301c217fa4972f8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M net/vmnet-bridged.m
M ui/cocoa.m
Log Message:
-----------
cocoa: Fix warnings about invalid prototype declarations
Fix the following Cocoa trivial warnings:
C compiler for the host machine: cc (clang 14.0.0 "Apple clang version 14.0.0
(clang-1400.0.29.202)")
Objective-C compiler for the host machine: clang (clang 14.0.0)
[100/334] Compiling Objective-C object libcommon.fa.p/net_vmnet-bridged.m.o
net/vmnet-bridged.m:40:31: warning: a function declaration without a
prototype is deprecated in all versions of C [-Wstrict-prototypes]
static char* get_valid_ifnames()
^
void
[742/1436] Compiling Objective-C object libcommon.fa.p/ui_cocoa.m.o
ui/cocoa.m:1937:22: warning: a function declaration without a prototype is
deprecated in all versions of C [-Wstrict-prototypes]
static int cocoa_main()
^
void
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20230425192820.34063-1-philmd@linaro.org>
Commit: 0baf54d0056979d6344b872a5b20acb6a5fd3cf8
https://github.com/qemu/qemu/commit/0baf54d0056979d6344b872a5b20acb6a5fd3cf8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M util/cacheflush.c
Log Message:
-----------
util/cacheflush: Use declarations from <OSCacheControl.h> on Darwin
Per the cache(3) man page, sys_icache_invalidate() and
sys_dcache_flush() are declared in <libkern/OSCacheControl.h>.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230605175647.88395-2-philmd@linaro.org>
Commit: bb6af0fa51cac875e5986aada0de339dcc94eca5
https://github.com/qemu/qemu/commit/bb6af0fa51cac875e5986aada0de339dcc94eca5
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M util/cacheflush.c
Log Message:
-----------
util/cacheflush: Avoid possible redundant dcache flush on Darwin
<libkern/OSCacheControl.h> describes sys_icache_invalidate() as
"equivalent to sys_cache_control(kCacheFunctionPrepareForExecution)",
having kCacheFunctionPrepareForExecution defined as:
/* Prepare memory for execution. This should be called
* after writing machine instructions to memory, before
* executing them. It syncs the dcache and icache. [...]
*/
Since the dcache is also sync'd, we can avoid the sys_dcache_flush()
call when both rx/rw pointers are equal.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20230605195911.96033-1-philmd@linaro.org>
Commit: ed3958910aef1461d99123c78afb1d70b74a83d0
https://github.com/qemu/qemu/commit/ed3958910aef1461d99123c78afb1d70b74a83d0
Author: Antonio Caggiano <quic_acaggian@quicinc.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M accel/hvf/hvf-all.c
Log Message:
-----------
accel/hvf: Report HV_DENIED error
On MacOS 11 and subsequent versions, in case the resulting binary is not
signed with the proper entitlement, handle and report the HV_DENIED
error.
Signed-off-by: Antonio Caggiano <quic_acaggian@quicinc.com>
Message-Id: <20230608123014.28715-1-quic_acaggian@quicinc.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 48b9e026791288088d1a9c807c36276c60e6573f
https://github.com/qemu/qemu/commit/48b9e026791288088d1a9c807c36276c60e6573f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/hppa/int_helper.c
M target/hppa/meson.build
Log Message:
-----------
target/hppa/meson: Only build int_helper.o with system emulation
int_helper.c only contains system emulation code:
remove the #ifdef'ry and move the file to the meson
softmmu source set.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230602223016.58647-1-philmd@linaro.org>
Commit: 3b8484c5d20a06944ebb3335c2f5e8014a5bf855
https://github.com/qemu/qemu/commit/3b8484c5d20a06944ebb3335c2f5e8014a5bf855
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/i386/cpu.h
M target/i386/helper.c
Log Message:
-----------
target/i386/helper: Remove do_cpu_sipi() stub for user-mode emulation
Since commit 604664726f ("target/i386: Restrict cpu_exec_interrupt()
handler to sysemu"), do_cpu_sipi() isn't called anymore on user
emulation. Remove the now pointless stub.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230602224628.59546-2-philmd@linaro.org>
Commit: 6d70b36b0207120461e586bf25d4e47baff1a0dc
https://github.com/qemu/qemu/commit/6d70b36b0207120461e586bf25d4e47baff1a0dc
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/i386/helper.c
Log Message:
-----------
target/i386/helper: Shuffle do_cpu_init()
Move the #ifdef'ry inside do_cpu_init() instead of
declaring an empty stub for user emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230602224628.59546-3-philmd@linaro.org>
Commit: f1cc7c28b611a5521e7e2e90d562e4b25af97d22
https://github.com/qemu/qemu/commit/f1cc7c28b611a5521e7e2e90d562e4b25af97d22
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M target/i386/helper.h
R target/i386/ops_sse_header.h
R target/i386/shift_helper_template.h
M target/i386/tcg/cc_helper.c
R target/i386/tcg/cc_helper_template.h
A target/i386/tcg/cc_helper_template.h.inc
M target/i386/tcg/int_helper.c
A target/i386/tcg/ops_sse_header.h.inc
A target/i386/tcg/shift_helper_template.h.inc
Log Message:
-----------
target/i386: Rename helper template headers as '.h.inc'
Since commit 139c1837db ("meson: rename included C source files
to .c.inc"), QEMU standard procedure for included C files is to
use *.c.inc.
Besides, since commit 6a0057aa22 ("docs/devel: make a statement
about includes") this is documented as the Coding Style:
If you do use template header files they should be named with
the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are
being included for expansion.
Therefore move the included templates in the tcg/ directory and
rename as '.h.inc'.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230608133108.72655-5-philmd@linaro.org>
Commit: 29770e09e4c877fa9cc6cedb93c5bcbf9ee10b50
https://github.com/qemu/qemu/commit/29770e09e4c877fa9cc6cedb93c5bcbf9ee10b50
Author: Patrick Venture <venture@google.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/i2c/i2c_mux_pca954x.c
Log Message:
-----------
hw/i2c: Enable an id for the pca954x devices
This allows the devices to be more readily found and specified.
Without setting the name field, they can only be found by device type
name, which doesn't let you specify the second of the same device type
behind a bus.
Tested: Verified that by default the device was findable with the name
'pca954x[77]', for an instance attached at that address.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20230322172136.48010-1-venture@google.com>
[PMD: Fix typo in property name]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: af33a321fabf9ae85781abe425acbfcbbbd99f9e
https://github.com/qemu/qemu/commit/af33a321fabf9ae85781abe425acbfcbbbd99f9e
Author: Niklas Cassel <niklas.cassel@wdc.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/ide/ahci.c
Log Message:
-----------
hw/ide/ahci: Remove stray backslash
This backslash obviously does not belong here, so remove it.
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-Id: <20230601134434.519805-2-nks@flawful.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 48143e0fd2a57371e939750c14f9dd622f5c73a1
https://github.com/qemu/qemu/commit/48143e0fd2a57371e939750c14f9dd622f5c73a1
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/scsi/megasas.c
Log Message:
-----------
hw/scsi/megasas: Silent GCC duplicated-cond warning
GCC9 is confused when building with CFLAG -O3:
hw/scsi/megasas.c: In function ‘megasas_scsi_realize’:
hw/scsi/megasas.c:2387:26: error: duplicated ‘if’ condition
[-Werror=duplicated-cond]
2387 | } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
hw/scsi/megasas.c:2385:19: note: previously used here
2385 | if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
cc1: all warnings being treated as errors
When this device was introduced in commit e8f943c3bcc, the author
cared about modularity, using a definition for the firmware limit.
However if the firmware limit isn't changed (MEGASAS_MAX_SGE = 128),
the code ends doing the same check twice.
Per the maintainer [*]:
> The original code assumed that one could change MFI_PASS_FRAME_SIZE,
> but it turned out not to be possible as it's being hardcoded in the
> drivers themselves (even though the interface provides mechanisms to
> query it). So we can remove the duplicate lines.
Add the 'MEGASAS_MIN_SGE' definition for the '64' magic value,
slightly rewrite the condition check to simplify a bit the logic
and remove the unnecessary / duplicated check.
[*]
https://lore.kernel.org/qemu-devel/e0029fc5-882f-1d63-15e3-1c3dbe9b6a2c@suse.de/
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Message-Id: <20230328210126.16282-1-philmd@linaro.org>
Commit: 8ff98e09f3ad447255368eccaac7412dd15e8777
https://github.com/qemu/qemu/commit/8ff98e09f3ad447255368eccaac7412dd15e8777
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/char/parallel.c
M include/hw/char/parallel.h
Log Message:
-----------
hw/char/parallel: Export struct ParallelState
Exporting ParallelState is a precondition for exporing TYPE_ISA_PARALLEL to be
performed in the next patch.
Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230612081238.1742-2-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 9cc44d9bd6fb8ceb75f8ae898a0d167f6305e511
https://github.com/qemu/qemu/commit/9cc44d9bd6fb8ceb75f8ae898a0d167f6305e511
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M MAINTAINERS
M hw/char/parallel-isa.c
M hw/char/parallel.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/isa/isa-superio.c
M hw/sparc64/sun4u.c
A include/hw/char/parallel-isa.h
M include/hw/char/parallel.h
Log Message:
-----------
hw/char/parallel-isa: Export struct ISAParallelState
Allows the struct to be embedded directly into device models without additional
allocation.
Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230612081238.1742-3-shentey@gmail.com>
[PMD: Update MAINTAINERS entry and use SPDX license identifier]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f80929f3af3a67a8111fbd9fc73705d4814bcf85
https://github.com/qemu/qemu/commit/f80929f3af3a67a8111fbd9fc73705d4814bcf85
Author: Joao Martins <joao.m.martins@oracle.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M include/exec/ram_addr.h
Log Message:
-----------
exec/ram_addr: Return number of dirty pages in
cpu_physical_memory_set_dirty_lebitmap()
In preparation for including the number of dirty pages in the
vfio_get_dirty_bitmap() tracepoint, return the number of dirty pages in
cpu_physical_memory_set_dirty_lebitmap() similar to
cpu_physical_memory_sync_dirty_bitmap().
To avoid counting twice when GLOBAL_DIRTY_RATE is enabled, stash the
number of bits set per bitmap quad in a variable (@nbits) and reuse it
there.
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230530180556.24441-2-joao.m.martins@oracle.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 6fe4f6c941923608027e10af5dd30f18d481f9b9
https://github.com/qemu/qemu/commit/6fe4f6c941923608027e10af5dd30f18d481f9b9
Author: Joao Martins <joao.m.martins@oracle.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M hw/vfio/common.c
M hw/vfio/trace-events
Log Message:
-----------
hw/vfio: Add number of dirty pages to vfio_get_dirty_bitmap tracepoint
Include the number of dirty pages on the vfio_get_dirty_bitmap tracepoint.
These are fetched from the newly added return value in
cpu_physical_memory_set_dirty_lebitmap().
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alex Williamson <alex.williamson@redhat.com>
Message-Id: <20230530180556.24441-3-joao.m.martins@oracle.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: b0182e537e5aba38031a5009cb16d5e924342458
https://github.com/qemu/qemu/commit/b0182e537e5aba38031a5009cb16d5e924342458
Author: Steve Sistare <steven.sistare@oracle.com>
Date: 2023-06-13 (Tue, 13 Jun 2023)
Changed paths:
M backends/hostmem-file.c
M include/exec/cpu-common.h
M include/exec/memory.h
M migration/ram.c
M qapi/migration.json
M softmmu/physmem.c
Log Message:
-----------
exec/memory: Introduce RAM_NAMED_FILE flag
migrate_ignore_shared() is an optimization that avoids copying memory
that is visible and can be mapped on the target. However, a
memory-backend-ram or a memory-backend-memfd block with the RAM_SHARED
flag set is not migrated when migrate_ignore_shared() is true. This is
wrong, because the block has no named backing store, and its contents will
be lost. To fix, ignore shared memory iff it is a named file. Define a
new flag RAM_NAMED_FILE to distinguish this case.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-Id: <1686151116-253260-1-git-send-email-steven.sistare@oracle.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 860029321d9ebdff47e89561de61e9441fead70a
https://github.com/qemu/qemu/commit/860029321d9ebdff47e89561de61e9441fead70a
Author: Tommy Wu <tommy.wu@sifive.com>
Date: 2023-06-14 (Wed, 14 Jun 2023)
Changed paths:
M hw/intc/riscv_aplic.c
Log Message:
-----------
hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
According to the `The RISC-V Advanced Interrupt Architecture`
document, if register `mmsiaddrcfgh` of the domain has bit L set
to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-Id: <20230609055936.3925438-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: be5e8563f737582276068c01f4dc4abfe484d0c3
https://github.com/qemu/qemu/commit/be5e8563f737582276068c01f4dc4abfe484d0c3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-14 (Wed, 14 Jun 2023)
Changed paths:
M MAINTAINERS
M accel/hvf/hvf-all.c
M backends/hostmem-file.c
M bsd-user/main.c
M hw/char/parallel-isa.c
M hw/char/parallel.c
M hw/i2c/i2c_mux_pca954x.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/ide/ahci.c
M hw/isa/isa-superio.c
M hw/scsi/megasas.c
M hw/sparc64/sun4u.c
M hw/vfio/common.c
M hw/vfio/trace-events
M include/exec/cpu-common.h
M include/exec/memory.h
M include/exec/ram_addr.h
A include/hw/char/parallel-isa.h
M include/hw/char/parallel.h
M linux-user/main.c
M migration/ram.c
M net/vmnet-bridged.m
M qapi/migration.json
M softmmu/physmem.c
M target/hppa/int_helper.c
M target/hppa/meson.build
M target/i386/cpu.h
M target/i386/helper.c
M target/i386/helper.h
R target/i386/ops_sse_header.h
R target/i386/shift_helper_template.h
M target/i386/tcg/cc_helper.c
R target/i386/tcg/cc_helper_template.h
A target/i386/tcg/cc_helper_template.h.inc
M target/i386/tcg/int_helper.c
A target/i386/tcg/ops_sse_header.h.inc
A target/i386/tcg/shift_helper_template.h.inc
M ui/cocoa.m
M util/cacheflush.c
Log Message:
-----------
Merge tag 'misc-20230613' of https://github.com/philmd/qemu into staging
Misc patches queue
- user emulation: Preserve environment variable order
- macos/darwin/hvf: Fix build warnings, slighly optimize DCache flush
- target/i386: Minor cleanups, rename template headers with '.inc' suffix
- target/hppa: Avoid building int_helper.o on user emulation
- hw: Add 'name' property to pca954x, export ISAParallelState, silent warnings
- hw/vfio: Trace number of bitmap dirty pages
- exec/memory: Introduce RAM_NAMED_FILE to distinct block without named backing
store
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmSINukACgkQ4+MsLN6t
# wN5fEQ/+PEC2CoBtl5aIODSowEyaFVmNTHZWQFmRAUlBoPR2rU7NEpnh3j4BJWSS
# aKc6MV4GDExKvMS5GujXiruS3kYMyWUHSG+nGUqrkBmbWn/2tZdWfIa0uT20CTr/
# nxu8TWM/EO+uzvYdyTNrXdkBOkU5eKfAqFGcWP7uLtRkjXpvu2YcPxrKswQUFpTh
# XH5sCh6esaBkMZLfsl0I4ZQLxtBWpM3EmaDvlDxftMt4OZ3kwbzC55xhN1uk6KxY
# iarkROM54vqU7ZC+vWH6fT18teLvKWXo+9F1iD/Qio88xRCH/kuQRWBM8+XR9IDe
# CKuaRrJ1nOmPojG3Xngd99eM7FPjh1FR6bR+L62cm8/PzuzbQi5VBIdJvxXfvoTL
# OjiXA3stOVB/jZg37IAeZB2X644d1GJXcjpExpU+mk7qdkaZC16HVOTRYYQF/wFF
# QBUntZ9Oz0+XRtt4PC8ckynq0p0uEA/mZ14jMm04AJ3W8XtnOk2xp5rFTn/f4tsI
# fJhqHxNhfet2sU17UI/pRw/h3Ulg0TmAdmMZnz3jUQ13/6E0//+a6dqQED/5HeG5
# 6UvUEUdGfvHuyE8l1UT4p93pBcyshMuaVFfutxKP9qYGPLhYeiCvms8KfdOWhTkA
# NC1JlOScwdEqkn1hyMCeJHEUpnuZHZeiOtn4VV4J/SwyxkzVRS8=
# =sUgM
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 13 Jun 2023 11:29:13 AM CEST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
* tag 'misc-20230613' of https://github.com/philmd/qemu:
exec/memory: Introduce RAM_NAMED_FILE flag
hw/vfio: Add number of dirty pages to vfio_get_dirty_bitmap tracepoint
exec/ram_addr: Return number of dirty pages in
cpu_physical_memory_set_dirty_lebitmap()
hw/char/parallel-isa: Export struct ISAParallelState
hw/char/parallel: Export struct ParallelState
hw/scsi/megasas: Silent GCC duplicated-cond warning
hw/ide/ahci: Remove stray backslash
hw/i2c: Enable an id for the pca954x devices
target/i386: Rename helper template headers as '.h.inc'
target/i386/helper: Shuffle do_cpu_init()
target/i386/helper: Remove do_cpu_sipi() stub for user-mode emulation
target/hppa/meson: Only build int_helper.o with system emulation
accel/hvf: Report HV_DENIED error
util/cacheflush: Avoid possible redundant dcache flush on Darwin
util/cacheflush: Use declarations from <OSCacheControl.h> on Darwin
cocoa: Fix warnings about invalid prototype declarations
linux-user, bsd-user: Preserve incoming order of environment variables in the
target
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7efd65423ab22e6f5890ca08ae40c84d6660242f
https://github.com/qemu/qemu/commit/7efd65423ab22e6f5890ca08ae40c84d6660242f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-14 (Wed, 14 Jun 2023)
Changed paths:
M accel/tcg/cpu-exec.c
M disas/riscv.c
M docs/system/riscv/virt.rst
M hw/intc/riscv_aplic.c
M hw/riscv/numa.c
M hw/riscv/opentitan.c
M hw/riscv/virt.c
M include/disas/dis-asm.h
M include/hw/core/cpu.h
M include/hw/riscv/opentitan.h
M include/qemu/log.h
M target/riscv/cpu.c
M target/riscv/cpu.h
A target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvzawrs.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/pmp.c
M target/riscv/pmp.h
M target/riscv/translate.c
M target/riscv/vector_helper.c
M util/log.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20230614' of
https://github.com/alistair23/qemu into staging
Second RISC-V PR for 8.1
* Skip Vector set tail when vta is zero
* Move zc* out of the experimental properties
* Mask the implicitly enabled extensions in isa_string based on priv version
* Rework CPU extension validation and validate MISA changes
* Fixup PMP TLB cacheing errors
* Writing to pmpaddr and MML/MMWP correctly triggers TLB flushes
* Fixup PMP bypass checks
* Deny access if access is partially inside a PMP entry
* Correct OpenTitanState parent type/size
* Fix QEMU crash when NUMA nodes exceed available CPUs
* Fix pointer mask transformation for vector address
* Updates and improvements for Smstateen
* Support disas for Zcm* extensions
* Support disas for Z*inx extensions
* Remove unused decomp_rv32/64 value for vector instructions
* Enable PC-relative translation
* Assume M-mode FW in pflash0 only when "-bios none"
* Support using pflash via -blockdev option
* Add vector registers to log
* Clean up reference of Vector MTYPE
* Remove the check for extra Vector tail elements
* Smepmp: Return error when access permission not allowed in PMP
* Fixes for smsiaddrcfg and smsiaddrcfgh in AIA
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmSJFRoACgkQr3yVEwxT
# gBMUkg/8Cuhqpx+zy7MeouVkyhEjUuhtCWyr0WVZBJzDkVEOrlY6TyR0hb5/o1Js
# LZf6ZMF6JQDN78bmUct8yFBZBGafey5tyonDCsnD7CNQuLPf2NSjTHhu9n5hKFqF
# F8Mpn9iFu6k1pr0iF7FbCccVWuDb3P4h2PaM0iFhmf4uz42BCMYdgJThhvv38xlt
# jr6A3dcjTpp8yB+iRCuhL2IU2XVee0XBiDUECqRXd0gmtOtqJNST8L+l8YkLy1VO
# WUMe8RCO6NMP7BLJ383WwCDeiFTo0mJebZQ0eR/G1xEhy7c8BBMh/CgQmq2F3wDZ
# Q0biaeozADgAaCC7aOAHI+1sAoMhOm1v2WhIVmh+XXUqT9856cKwc7DUPBmzb9Sj
# N5Zh+t9WCnZG7qpfxvkDF0Y/aRODMHZ1BW5L/ky9yBtyuRwXOJ6VycZTFyRkSwnN
# Gd/s9IClDOP1IP5s4TSMGGdelk4lH97x7fZE/2hxn59lp761JtMxbaEceBtqaBh8
# zNMTNN/KHs8LeiIBI2ZZ+nQav452Y6XYBivQ7OdsI8xkjnjG9gfgXXjvX1TIh0ow
# Hy5ZxtAtjXty49Gmjkx5VcBx4auJcnRDlLTzoZjTxq1te+gEWpw6O1EsEKasVLZe
# uN6PxTOxS3nHvRvPgQc1xNUdhDRqBaYsju6b9YmMxz1uefAjGM0=
# =fOTc
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 14 Jun 2023 03:17:14 AM CEST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu: (60
commits)
hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
target/riscv: Smepmp: Return error when access permission not allowed in PMP
target/riscv/vector_helper.c: Remove the check for extra tail elements
target/riscv/vector_helper.c: clean up reference of MTYPE
target/riscv: Fix initialized value for cur_pmmask
util/log: Add vector registers to log
docs/system: riscv: Add pflash usage details
riscv/virt: Support using pflash via -blockdev option
hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
target/riscv: Remove pc_succ_insn from DisasContext
target/riscv: Enable PC-relative translation
target/riscv: Use true diff for gen_pc_plus_diff
target/riscv: Change gen_set_pc_imm to gen_update_pc
target/riscv: Change gen_goto_tb to work on displacements
target/riscv: Introduce cur_insn_len into DisasContext
target/riscv: Fix target address to update badaddr
disas/riscv.c: Remove redundant parentheses
disas/riscv.c: Fix lines with over 80 characters
disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
disas/riscv.c: Support disas for Z*inx extensions
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/fdd0df5340a8...7efd65423ab2