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[Qemu-commits] [qemu/qemu] 243705: target/arm: Fix return value from LDS
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 243705: target/arm: Fix return value from LDSMIN/LDSMAX 8/... |
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Date: |
Mon, 19 Jun 2023 09:58:26 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 243705aa6ea3465b20e9f5a8bfcf36d3153f3c10
https://github.com/qemu/qemu/commit/243705aa6ea3465b20e9f5a8bfcf36d3153f3c10
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
The atomic memory operations are supposed to return the old memory
data value in the destination register. This value is not
sign-extended, even if the operation is the signed minimum or
maximum. (In the pseudocode for the instructions the returned data
value is passed to ZeroExtend() to create the value in the register.)
We got this wrong because we were doing a 32-to-64 zero extend on the
result for 8 and 16 bit data values, rather than the correct amount
of zero extension.
Fix the bug by using ext8u and ext16u for the MO_8 and MO_16 data
sizes rather than ext32u.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-2-peter.maydell@linaro.org
Commit: 7e2788471f9e079fff696a694721a7d41a451839
https://github.com/qemu/qemu/commit/7e2788471f9e079fff696a694721a7d41a451839
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Return correct result for LDG when ATA=0
The LDG instruction loads the tag from a memory address (identified
by [Xn + offset]), and then merges that tag into the destination
register Xt. We implemented this correctly for the case when
allocation tags are enabled, but didn't get it right when ATA=0:
instead of merging the tag bits into Xt, we merged them into the
memory address [Xn + offset] and then set Xt to that.
Merge the tag bits into the old Xt value, as they should be.
Cc: qemu-stable@nongnu.org
Fixes: c15294c1e36a7dd9b25 ("target/arm: Implement LDG, STG, ST2G instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 99bb43c0ff7c72ef7fa5035ff8e6151b1c08ce68
https://github.com/qemu/qemu/commit/99bb43c0ff7c72ef7fa5035ff8e6151b1c08ce68
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode
In disas_ldst_reg_imm9() we missed one place where a call to
a gen_mte_check* function should now be passed the memop we
have created rather than just being passed the size. Fix this.
Fixes: 0a9091424d ("target/arm: Pass memop to gen_mte_check1*")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 68496d4172296ff04b90e3dfbee13316615d8167
https://github.com/qemu/qemu/commit/68496d4172296ff04b90e3dfbee13316615d8167
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores
In the recent refactoring we missed a few places which should be
calling finalize_memop_asimd() for ASIMD loads and stores but
instead are just calling finalize_memop(); fix these.
For the disas_ldst_single_struct() and disas_ldst_multiple_struct()
cases, this is not a behaviour change because there the size
is never MO_128 and the two finalize functions do the same thing.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7fefc70661a70ba512a10ebefda0c9c29454d1e1
https://github.com/qemu/qemu/commit/7fefc70661a70ba512a10ebefda0c9c29454d1e1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert hint instruction space to decodetree
Convert the various instructions in the hint instruction space
to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-3-peter.maydell@linaro.org
Commit: afcd5df54c5bb9ffbfadf379cca4ecf20ef9b2dc
https://github.com/qemu/qemu/commit/afcd5df54c5bb9ffbfadf379cca4ecf20ef9b2dc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert barrier insns to decodetree
Convert the insns in the "Barriers" instruction class to
decodetree: CLREX, DSB, DMB, ISB and SB.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-4-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: d78b662f28ac6cdab6ad969bb23a10e0e3cf1c32
https://github.com/qemu/qemu/commit/d78b662f28ac6cdab6ad969bb23a10e0e3cf1c32
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree
Convert the CFINV, XAFLAG and AXFLAG insns to decodetree.
The old decoder handles these in handle_msr_i(), but
the architecture defines them as separate instructions
from MSR (immediate).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-5-peter.maydell@linaro.org
Commit: 45d063d1630486491e22ace34a1d87d71c0eed35
https://github.com/qemu/qemu/commit/45d063d1630486491e22ace34a1d87d71c0eed35
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert MSR (immediate) to decodetree
Convert the MSR (immediate) insn to decodetree. Our implementation
has basically no commonality between the different destinations,
so we decode the destination register in a64.decode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-6-peter.maydell@linaro.org
Commit: 6e3c8049ad90951e81077d594f2cfe8c10047213
https://github.com/qemu/qemu/commit/6e3c8049ad90951e81077d594f2cfe8c10047213
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree
Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are
all essentially the same instruction (system register access).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-7-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: a97d3c18f61fd307bffd3579ba35fccd2d88aeb1
https://github.com/qemu/qemu/commit/a97d3c18f61fd307bffd3579ba35fccd2d88aeb1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert exception generation instructions to decodetree
Convert the exception generation instructions SVC, HVC, SMC, BRK and
HLT to decodetree.
The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and
DCPS3 just in order to then make them UNDEF; as with DRPS, we don't
bother to decode them, but document the patterns in a64.decode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org
Commit: 84693e67fa5a6ffa14133c3038c57988b71dd135
https://github.com/qemu/qemu/commit/84693e67fa5a6ffa14133c3038c57988b71dd135
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert load/store exclusive and ordered to decodetree
Convert the instructions in the load/store exclusive (STXR,
STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR,
LDAR, LDLAR) to decodetree.
Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding
in the legacy decoder where we were not checking that the RES1 bits
in the Rs and Rt2 fields were set.
The new function ldst_iss_sf() is equivalent to the existing
disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field
rather than taking an undecoded two-bit opc field and extracting
'ext' from it. Once all the loads and stores have been converted
to decodetree disas_ldst_compute_iss_sf() will be unused and
can be deleted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org
Commit: e8a149a359f4d518bdd5dac320fc16ef0909dc77
https://github.com/qemu/qemu/commit/e8a149a359f4d518bdd5dac320fc16ef0909dc77
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP),
compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and
swap (CAS, CASA, CASAL, CASL) instructions to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org
Commit: a752c2f45968951c99f35130e76b191dedebcee7
https://github.com/qemu/qemu/commit/a752c2f45968951c99f35130e76b191dedebcee7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert load reg (literal) group to decodetree
Convert the "Load register (literal)" instruction class to
decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-11-peter.maydell@linaro.org
Commit: 8c212eb65944097d70a28195985acd0ba2a016bc
https://github.com/qemu/qemu/commit/8c212eb65944097d70a28195985acd0ba2a016bc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert load/store-pair to decodetree
Convert the load/store register pair insns (LDP, STP,
LDNP, STNP, LDPSW, STGP) to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230602155223.2040685-12-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 60cd7ba9c5ed0f19119ed5c385235a4500c120b6
https://github.com/qemu/qemu/commit/60cd7ba9c5ed0f19119ed5c385235a4500c120b6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert ld/st reg+imm9 insns to decodetree
Convert the load and store instructions which use a 9-bit
immediate offset to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-13-peter.maydell@linaro.org
Commit: 61edd8f878ec3eb51ff3cc5eb5a5e96cb64f534b
https://github.com/qemu/qemu/commit/61edd8f878ec3eb51ff3cc5eb5a5e96cb64f534b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert LDR/STR with 12-bit immediate to decodetree
Convert the LDR and STR instructions which use a 12-bit immediate
offset to decodetree. We can reuse the existing LDR and STR
trans functions for these.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-14-peter.maydell@linaro.org
Commit: f36bf0c14a223b38a08fbb7e53e1a6a700735de9
https://github.com/qemu/qemu/commit/f36bf0c14a223b38a08fbb7e53e1a6a700735de9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert LDR/STR reg+reg to decodetree
Convert the LDR and STR instructions which take a register
plus register offset to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-15-peter.maydell@linaro.org
Commit: 54a9ab74edd34c516552113a89bfc5eb1ec61c8e
https://github.com/qemu/qemu/commit/54a9ab74edd34c516552113a89bfc5eb1ec61c8e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert atomic memory ops to decodetree
Convert the insns in the atomic memory operations group to
decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-16-peter.maydell@linaro.org
Commit: be23a049ec30aff1e3627eb1afdf095d940eae4a
https://github.com/qemu/qemu/commit/be23a049ec30aff1e3627eb1afdf095d940eae4a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert load (pointer auth) insns to decodetree
Convert the instructions in the load/store register (pointer
authentication) group ot decodetree: LDRAA, LDRAB.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-17-peter.maydell@linaro.org
Commit: 2521b6073b7b4b505533a941d4f9600f7585dc78
https://github.com/qemu/qemu/commit/2521b6073b7b4b505533a941d4f9600f7585dc78
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert LDAPR/STLR (imm) to decodetree
Convert the instructions in the LDAPR/STLR (unscaled immediate)
group to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-18-peter.maydell@linaro.org
Commit: e25ba1fa0b95316c69573bb2778f4549df097966
https://github.com/qemu/qemu/commit/e25ba1fa0b95316c69573bb2778f4549df097966
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert load/store (multiple structures) to decodetree
Convert the instructions in the ASIMD load/store multiple structures
instruction classes to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-19-peter.maydell@linaro.org
Commit: 3d507213264f3af221598f9af12b5e6212bf403a
https://github.com/qemu/qemu/commit/3d507213264f3af221598f9af12b5e6212bf403a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert load/store single structure to decodetree
Convert the ASIMD load/store single structure insns to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230602155223.2040685-20-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 946ccfd590f65c09211c4899446e07ef589bc093
https://github.com/qemu/qemu/commit/946ccfd590f65c09211c4899446e07ef589bc093
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert load/store tags insns to decodetree
Convert the instructions in the load/store memory tags instruction
group to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-21-peter.maydell@linaro.org
Commit: f837b468cdaa7e736b5385c7dc4f8c5adcad3bf1
https://github.com/qemu/qemu/commit/f837b468cdaa7e736b5385c7dc4f8c5adcad3bf1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M hw/intc/allwinner-a10-pic.c
Log Message:
-----------
hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner
A10 PIC model; however in the process we introduced a regression.
This is because the old code was robust against the incoming 'level'
argument being something other than 0 or 1, whereas the new code was
not.
In particular, the allwinner-sdhost code treats its IRQ line
as 0-vs-non-0 rather than 0-vs-1, so when the SD controller
set its IRQ line for any reason other than transmit the
interrupt controller would ignore it. The observed effect
was a guest timeout when rebooting the guest kernel.
Handle level values other than 0 or 1, to restore the old
behaviour.
Fixes: 2c5fa0778c3b430 ("hw/intc/allwinner-a10-pic: Don't use
set_bit()/clear_bit()")
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20230606104609.3692557-2-peter.maydell@linaro.org
Commit: 22c81783c9458f2b41d554e0172c9d0fcf6da4cc
https://github.com/qemu/qemu/commit/22c81783c9458f2b41d554e0172c9d0fcf6da4cc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M hw/sd/allwinner-sdhost.c
Log Message:
-----------
hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels
QEMU allows qemu_irq lines to transfer arbitrary integers. However
the convention is that for a simple IRQ line the values transferred
are always 0 and 1. The A10 SD controller device instead assumes a
0-vs-non-0 convention, which happens to work with the interrupt
controller it is wired up to.
Coerce the value to boolean to follow our usual convention.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20230606104609.3692557-3-peter.maydell@linaro.org
Commit: d2f9a79a8cf6ab992e1d0f27ad05b3e582d2b18a
https://github.com/qemu/qemu/commit/d2f9a79a8cf6ab992e1d0f27ad05b3e582d2b18a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M hw/timer/nrf51_timer.c
Log Message:
-----------
hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop
The nrf51_timer has a free-running counter which we implement using
the pattern of using two fields (update_counter_ns, counter) to track
the last point at which we calculated the counter value, and the
counter value at that time. Then we can find the current counter
value by converting the difference in wall-clock time between then
and now to a tick count that we need to add to the counter value.
Unfortunately the nrf51_timer's implementation of this has a bug
which means it loses time every time update_counter() is called.
After updating s->counter it always sets s->update_counter_ns to
'now', even though the actual point when s->counter hit the new value
will be some point in the past (half a tick, say). In the worst case
(guest code in a tight loop reading the counter, icount mode) the
counter is continually queried less than a tick after it was last
read, so s->counter never advances but s->update_counter_ns does, and
the guest never makes forward progress.
The fix for this is to only advance update_counter_ns to the
timestamp of the last tick, not all the way to 'now'. (This is the
pattern used in hw/misc/mps2-fpgaio.c's counter.)
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20230606134917.3782215-1-peter.maydell@linaro.org
Commit: 93faf3b9c9396bc06da4a380de67637334b1143d
https://github.com/qemu/qemu/commit/93faf3b9c9396bc06da4a380de67637334b1143d
Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M hw/arm/Kconfig
Log Message:
-----------
hw/arm/Kconfig: sbsa-ref uses Bochs display
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230607092112.655098-1-marcin.juszkiewicz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bd96e10071e4d44eea9b9c8888ed12d2f9d8fae9
https://github.com/qemu/qemu/commit/bd96e10071e4d44eea9b9c8888ed12d2f9d8fae9
Author: Martin Kaiser <martin@kaiser.cx>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M hw/char/imx_serial.c
M include/hw/char/imx_serial.h
Log Message:
-----------
imx_serial: set wake bit when we receive a data byte
The Linux kernel added a flood check for RX data recently in commit
496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This
check uses the wake bit in the UART status register 2. The wake bit
indicates that the receiver detected a start bit on the RX line. If the
kernel sees a number of RX interrupts without the wake bit being set, it
treats this as spurious data and resets the UART port. imx_serial does
never set the wake bit and triggers the kernel's flood check.
This patch adds support for the wake bit. wake is set when we receive a
new character (it's not set for break events). It seems that wake is
cleared by the kernel driver, the hardware does not have to clear it
automatically after data was read.
The wake bit can be configured as an interrupt source. Support this
mechanism as well.
Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ff49fb950dd89da21b6ab77f39d7bd5be2a63542
https://github.com/qemu/qemu/commit/ff49fb950dd89da21b6ab77f39d7bd5be2a63542
Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M docs/system/arm/sbsa.rst
Log Message:
-----------
docs: sbsa: document board to firmware interface
We plan to add more hardware information into DeviceTree to limit amount
of hardcoded values in firmware.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20230531171834.236569-1-marcin.juszkiewicz@linaro.org
[PMM: fix format nits, add text about platform version fields from
a comment in the C source file]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 089ec16010e51ee4f5d57c154d3d306e6f564757
https://github.com/qemu/qemu/commit/089ec16010e51ee4f5d57c154d3d306e6f564757
Author: Sergey Kambalin <sergey.kambalin@auriga.com>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
A include/hw/misc/raspberrypi-fw-defs.h
Log Message:
-----------
hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h'
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230612223456.33824-2-philmd@linaro.org
Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com>
[PMD: Split from bigger patch: 1/4]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2519182666666a8c08bbcdb053464459e93a2451
https://github.com/qemu/qemu/commit/2519182666666a8c08bbcdb053464459e93a2451
Author: Sergey Kambalin <sergey.kambalin@auriga.com>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M hw/misc/bcm2835_property.c
Log Message:
-----------
hw/misc/bcm2835_property: Use 'raspberrypi-fw-defs.h' definitions
Replace magic property values by a proper definition,
removing redundant comments.
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230612223456.33824-3-philmd@linaro.org
Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com>
[PMD: Split from bigger patch: 2/4]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5dc496363a5bd7bec9cf0287cfbece9b94bcfa9a
https://github.com/qemu/qemu/commit/5dc496363a5bd7bec9cf0287cfbece9b94bcfa9a
Author: Sergey Kambalin <sergey.kambalin@auriga.com>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M hw/misc/bcm2835_property.c
M include/hw/arm/raspi_platform.h
Log Message:
-----------
hw/misc/bcm2835_property: Replace magic frequency values by definitions
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230612223456.33824-4-philmd@linaro.org
Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com>
[PMD: Split from bigger patch: 4/4]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 074259c0f2ac40042dce766d870318cc22f388eb
https://github.com/qemu/qemu/commit/074259c0f2ac40042dce766d870318cc22f388eb
Author: Sergey Kambalin <sergey.kambalin@auriga.com>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M hw/misc/bcm2835_property.c
M include/hw/arm/raspi_platform.h
Log Message:
-----------
hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230612223456.33824-5-philmd@linaro.org
Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com>
[PMD: Split from bigger patch: 3/4]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[PMM: added a comment about RPI_FIRMWARE_CORE_CLK_RATE
really being SoC-specific]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 48ab886d3da4f3ab94f79f6c0f8b4535b446bbfd
https://github.com/qemu/qemu/commit/48ab886d3da4f3ab94f79f6c0f8b4535b446bbfd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-19 (Mon, 19 Jun 2023)
Changed paths:
M docs/system/arm/sbsa.rst
M hw/arm/Kconfig
M hw/char/imx_serial.c
M hw/intc/allwinner-a10-pic.c
M hw/misc/bcm2835_property.c
M hw/sd/allwinner-sdhost.c
M hw/timer/nrf51_timer.c
M include/hw/arm/raspi_platform.h
M include/hw/char/imx_serial.h
A include/hw/misc/raspberrypi-fw-defs.h
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
Merge tag 'pull-target-arm-20230619' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
* Return correct result for LDG when ATA=0
* Conversion of system insns, loads and stores to decodetree
* hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
* hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels
* hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop
* hw/arm/Kconfig: sbsa-ref uses Bochs display
* imx_serial: set wake bit when we receive a data byte
* docs: sbsa: document board to firmware interface
* hw/misc/bcm2835_property: avoid hard-coded constants
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# gpg: Signature made Mon 19 Jun 2023 04:27:41 PM CEST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20230619' of
https://git.linaro.org/people/pmaydell/qemu-arm: (33 commits)
hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property
hw/misc/bcm2835_property: Replace magic frequency values by definitions
hw/misc/bcm2835_property: Use 'raspberrypi-fw-defs.h' definitions
hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h'
docs: sbsa: document board to firmware interface
imx_serial: set wake bit when we receive a data byte
hw/arm/Kconfig: sbsa-ref uses Bochs display
hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop
hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels
hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
target/arm: Convert load/store tags insns to decodetree
target/arm: Convert load/store single structure to decodetree
target/arm: Convert load/store (multiple structures) to decodetree
target/arm: Convert LDAPR/STLR (imm) to decodetree
target/arm: Convert load (pointer auth) insns to decodetree
target/arm: Convert atomic memory ops to decodetree
target/arm: Convert LDR/STR reg+reg to decodetree
target/arm: Convert LDR/STR with 12-bit immediate to decodetree
target/arm: Convert ld/st reg+imm9 insns to decodetree
target/arm: Convert load/store-pair to decodetree
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/e3660cc1e3cb...48ab886d3da4