[Qemu-commits] [qemu/qemu] 4d2b2e: target/tricore: Introduce ISA 1.6.2 f

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[Qemu-commits] [qemu/qemu] 4d2b2e: target/tricore: Introduce ISA 1.6.2 f

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] 4d2b2e: target/tricore: Introduce ISA 1.6.2 feature
Date:	Wed, 21 Jun 2023 11:09:20 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4d2b2e766a5a60afdfa85652a328c967c248d47f
      
https://github.com/qemu/qemu/commit/4d2b2e766a5a60afdfa85652a328c967c248d47f
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/cpu.c
    M target/tricore/cpu.h

  Log Message:
  -----------
  target/tricore: Introduce ISA 1.6.2 feature

we also introduce the tc37x CPU that implements that ISA version.

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-2-kbastian@mail.uni-paderborn.de>


  Commit: fd6f446a5e34f160cbdc9bb300d326cec0eca6c6
      
https://github.com/qemu/qemu/commit/fd6f446a5e34f160cbdc9bb300d326cec0eca6c6
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c
    M target/tricore/tricore-opcodes.h

  Log Message:
  -----------
  target/tricore: Add popcnt.w insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-3-kbastian@mail.uni-paderborn.de>


  Commit: 73f874d9fe67bc0395d629d4d1ce083f61605ba5
      
https://github.com/qemu/qemu/commit/73f874d9fe67bc0395d629d4d1ce083f61605ba5
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c
    M target/tricore/tricore-opcodes.h

  Log Message:
  -----------
  target/tricore: Add LHA insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-4-kbastian@mail.uni-paderborn.de>


  Commit: dc0b4368be92d85fc9fb2d48922149759c1f7804
      
https://github.com/qemu/qemu/commit/dc0b4368be92d85fc9fb2d48922149759c1f7804
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/helper.h
    M target/tricore/op_helper.c
    M target/tricore/translate.c
    M target/tricore/tricore-opcodes.h

  Log Message:
  -----------
  target/tricore: Add crc32l.w insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-5-kbastian@mail.uni-paderborn.de>


  Commit: 0eaafe33d03447f36ff152010836d501ba68c710
      
https://github.com/qemu/qemu/commit/0eaafe33d03447f36ff152010836d501ba68c710
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/helper.h
    M target/tricore/op_helper.c
    M target/tricore/translate.c
    M target/tricore/tricore-opcodes.h

  Log Message:
  -----------
  target/tricore: Add crc32.b insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-6-kbastian@mail.uni-paderborn.de>


  Commit: 4e3377bb5abe8914eec0650730536d5d48e22008
      
https://github.com/qemu/qemu/commit/4e3377bb5abe8914eec0650730536d5d48e22008
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/helper.h
    M target/tricore/op_helper.c
    M target/tricore/translate.c
    M target/tricore/tricore-opcodes.h

  Log Message:
  -----------
  target/tricore: Add shuffle insn

this is based on code by volumit (https://github.com/volumit/qemu/).

Reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
and https://gitlab.com/qemu-project/qemu/-/issues/1452.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-7-kbastian@mail.uni-paderborn.de>


  Commit: 3b5d136db6484f2b625fb98cce4fd8b7ac26e348
      
https://github.com/qemu/qemu/commit/3b5d136db6484f2b625fb98cce4fd8b7ac26e348
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Implement SYCSCALL insn

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1452
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-8-kbastian@mail.uni-paderborn.de>


  Commit: 0b9f9b63c2d1e26cfe4e593f384898837c7c941f
      
https://github.com/qemu/qemu/commit/0b9f9b63c2d1e26cfe4e593f384898837c7c941f
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c
    M target/tricore/tricore-opcodes.h

  Log Message:
  -----------
  target/tricore: Add DISABLE insn variant

this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield
changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext
as with the other DISABLE insn.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-9-kbastian@mail.uni-paderborn.de>


  Commit: d34b092cab606a47a0d76edde45aab7100bb2435
      
https://github.com/qemu/qemu/commit/d34b092cab606a47a0d76edde45aab7100bb2435
  Author: Siqi Chen <coc.cyqh@gmail.com>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Fix out-of-bounds index in imask instruction

When translating  "imask" instruction of Tricore architecture, QEMU did not 
check whether the register index was out of bounds, resulting in a 
global-buffer-overflow.

Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1698
Reported-by: Siqi Chen <coc.cyqh@gmail.com>
Signed-off-by: Siqi Chen <coc.cyqh@gmail.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230612065633.149152-1-coc.cyqh@gmail.com>
Message-Id: <20230612113245.56667-2-kbastian@mail.uni-paderborn.de>


  Commit: 5434557ffc5b46f178ccf325517db2b1f5e2c037
      
https://github.com/qemu/qemu/commit/5434557ffc5b46f178ccf325517db2b1f5e2c037
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/op_helper.c

  Log Message:
  -----------
  target/tricore: Correctly fix saving PSW.CDE to CSA on call

we don't want to save PSW.CDC to the CSA, but PSW.CDE must be saved.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1699
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230612113245.56667-3-kbastian@mail.uni-paderborn.de>


  Commit: 6991777ec4b2a344d47bddec62744bedd9883d78
      
https://github.com/qemu/qemu/commit/6991777ec4b2a344d47bddec62744bedd9883d78
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs

some insns were not checking if an even index was used to access a 64
bit register. In the worst case that could lead to a buffer overflow as
reported in https://gitlab.com/qemu-project/qemu/-/issues/1698.

Reported-by: Siqi Chen <coc.cyqh@gmail.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230612113245.56667-4-kbastian@mail.uni-paderborn.de>


  Commit: 82736612e75b84f51d8f3529cb35fa3835de5741
      
https://github.com/qemu/qemu/commit/82736612e75b84f51d8f3529cb35fa3835de5741
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/op_helper.c

  Log Message:
  -----------
  target/tricore: Fix helper_ret() not correctly restoring PSW

We are always taking the TRICORE_FEATURE_13 branch as every CPU has 
TRICORE_FEATURE_13.
For CPUs with ISA > 1.3 we have to take the else branch.

We fix this by inverting the condition. We check for
TRICORE_FEATURE_131, which every CPU except TRICORE_FEATURE_13 CPUs
have.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1700
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230612113245.56667-5-kbastian@mail.uni-paderborn.de>


  Commit: 8da70480f59b4fd423918ac756747c1e35f6f53a
      
https://github.com/qemu/qemu/commit/8da70480f59b4fd423918ac756747c1e35f6f53a
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Fix RR_JLI clobbering reg A[11]

if A[r1] == A[11], then we would overwrite the destination address of
the jump with the return address.

Reported-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-2-kbastian@mail.uni-paderborn.de>


  Commit: 1706e04f6e807431b460b4109ab65bb469adc53a
      
https://github.com/qemu/qemu/commit/1706e04f6e807431b460b4109ab65bb469adc53a
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Introduce DISAS_TARGET_EXIT

this replaces all calls to tcg_gen_exit_tb() and moves them to
tricore_tb_stop().

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-3-kbastian@mail.uni-paderborn.de>


  Commit: 2dbd73bf17f4c6bf016709d995ea46477cb6133c
      
https://github.com/qemu/qemu/commit/2dbd73bf17f4c6bf016709d995ea46477cb6133c
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: ENABLE exit to main-loop

so we can recognize exceptions after re-enabling interrupts.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-4-kbastian@mail.uni-paderborn.de>


  Commit: d8f466af7cad3a997c3f9d0396f2a63826fee239
      
https://github.com/qemu/qemu/commit/d8f466af7cad3a997c3f9d0396f2a63826fee239
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr()

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-5-kbastian@mail.uni-paderborn.de>


  Commit: 878d1b6a90173d61859f1b5083266d2bbc3db17c
      
https://github.com/qemu/qemu/commit/878d1b6a90173d61859f1b5083266d2bbc3db17c
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/cpu.h
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Introduce priv tb flag

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-6-kbastian@mail.uni-paderborn.de>


  Commit: 57b9c589b621b40f3a81662ad1aa960ab6a60497
      
https://github.com/qemu/qemu/commit/57b9c589b621b40f3a81662ad1aa960ab6a60497
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Implement privilege level for all insns

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-7-kbastian@mail.uni-paderborn.de>


  Commit: 19a18edd8860064d3dbe71bc5315347bcfeb4c24
      
https://github.com/qemu/qemu/commit/19a18edd8860064d3dbe71bc5315347bcfeb4c24
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Honour privilege changes on PSW write

the CPU can change the privilege level by writing the corresponding bits
in PSW. If this happens all instructions after this 'mtcr' in the TB are
translated with the wrong privilege level. So we have to exit to the
cpu_loop() and start translating again with the new privilege level.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-8-kbastian@mail.uni-paderborn.de>


  Commit: a9c37abdff65a07d0191123a21d318c4d8cc7f33
      
https://github.com/qemu/qemu/commit/a9c37abdff65a07d0191123a21d318c4d8cc7f33
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Fix ICR.IE offset in RESTORE insn

from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU. We also need to exit this tb here, as we might have enabled
interrupts.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-9-kbastian@mail.uni-paderborn.de>


  Commit: 67fe6ae41da64368bc4936b196fee2bf61f8c720
      
https://github.com/qemu/qemu/commit/67fe6ae41da64368bc4936b196fee2bf61f8c720
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M target/tricore/cpu.c
    M target/tricore/cpu.h
    M target/tricore/helper.h
    M target/tricore/op_helper.c
    M target/tricore/translate.c
    M target/tricore/tricore-opcodes.h

  Log Message:
  -----------
  Merge tag 'pull-tricore-20230621-1' of https://github.com/bkoppelmann/qemu 
into staging

- Implement privilege levels for TriCore
- Fix missing REG_PAIR() for insns using two 32 regs
- Fix erroneously saving PSW.CDC on CALL insns
- Added some missing v1.6.2 insns

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* tag 'pull-tricore-20230621-1' of https://github.com/bkoppelmann/qemu:
  target/tricore: Fix ICR.IE offset in RESTORE insn
  target/tricore: Honour privilege changes on PSW write
  target/tricore: Implement privilege level for all insns
  target/tricore: Introduce priv tb flag
  target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr()
  target/tricore: ENABLE exit to main-loop
  target/tricore: Introduce DISAS_TARGET_EXIT
  target/tricore: Fix RR_JLI clobbering reg A[11]
  target/tricore: Fix helper_ret() not correctly restoring PSW
  target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs
  target/tricore: Correctly fix saving PSW.CDE to CSA on call
  target/tricore: Fix out-of-bounds index in imask instruction
  target/tricore: Add DISABLE insn variant
  target/tricore: Implement SYCSCALL insn
  target/tricore: Add shuffle insn
  target/tricore: Add crc32.b insn
  target/tricore: Add crc32l.w insn
  target/tricore: Add LHA insn
  target/tricore: Add popcnt.w insn
  target/tricore: Introduce ISA 1.6.2 feature

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/c5ffd16ba4c8...67fe6ae41da6
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