[Qemu-commits] [qemu/qemu] b9f335: target/arm: Add isar_feature_aa64_rme

[Richard Henderson]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: b9f335c24705883391ea52035c9b2229e6992eee
      
https://github.com/qemu/qemu/commit/b9f335c24705883391ea52035c9b2229e6992eee
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add isar_feature_aa64_rme

Add the missing field for ID_AA64PFR0, and the predicate.
Disable it if EL3 is forced off by the board or command-line.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: aa3cc42c016116615b80359ab4dd8a934339aec5
      
https://github.com/qemu/qemu/commit/aa3cc42c016116615b80359ab4dd8a934339aec5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Update SCR and HCR for RME

Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF
to be set, and invalidate TLBs when NSE changes.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 87bfbfe7e595372251037c28223919659a294fd3
      
https://github.com/qemu/qemu/commit/87bfbfe7e595372251037c28223919659a294fd3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: SCR_EL3.NS may be RES1

With RME, SEL2 must also be present to support secure state.
The NS bit is RES1 if SEL2 is not present.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ef1febe758c893dfc2164c5324bbbe5ba4916413
      
https://github.com/qemu/qemu/commit/ef1febe758c893dfc2164c5324bbbe5ba4916413
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add RME cpregs

This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS,
RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5d28ac0cf7a5cd91f03da658edd6e934c5a431bd
      
https://github.com/qemu/qemu/commit/5d28ac0cf7a5cd91f03da658edd6e934c5a431bd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Introduce ARMSecuritySpace

Introduce both the enumeration and functions to retrieve
the current state, and state outside of EL3.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4d6e1c6495f483e8c48526189c4c6984b44365fc
      
https://github.com/qemu/qemu/commit/4d6e1c6495f483e8c48526189c4c6984b44365fc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M include/exec/memattrs.h

  Log Message:
  -----------
  include/exec/memattrs: Add two bits of space to MemTxAttrs

We will need 2 bits to represent ARMSecurityState.

Do not attempt to replace or widen secure, even though it
logically overlaps the new field -- there are uses within
e.g. hw/block/pflash_cfi01.c, which don't know anything
specific about ARM.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d38fa9670d14331fc766dfc15b2bc6628d0149d0
      
https://github.com/qemu/qemu/commit/d38fa9670d14331fc766dfc15b2bc6628d0149d0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx

It will be helpful to have ARMMMUIdx_Phys_* to be in the same
relative order as ARMSecuritySpace enumerators. This requires
the adjustment to the nstable check. While there, check for being
in secure state rather than rely on clearing the low bit making
no change to non-secure state.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bb5cc2c860c4d359e107ede2464dfe5cd297f16b
      
https://github.com/qemu/qemu/commit/bb5cc2c860c4d359e107ede2464dfe5cd297f16b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}

With FEAT_RME, there are four physical address spaces.
For now, just define the symbols, and mention them in
the same spots as the other Phys indexes in ptw.c.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 86a438b462406c7944be1fea8b027604e85253ff
      
https://github.com/qemu/qemu/commit/86a438b462406c7944be1fea8b027604e85253ff
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Remove __attribute__((nonnull)) from ptw.c

This was added in 7e98e21c098 as part of a reorg in which
one of the argument had been legally NULL, and this caught
actual instances.  Now that the reorg is complete, this
serves little purpose.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 90c6629393e0d7121c84033b3aa886fd0662a1c7
      
https://github.com/qemu/qemu/commit/90c6629393e0d7121c84033b3aa886fd0662a1c7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Pipe ARMSecuritySpace through ptw.c

Add input and output space members to S1Translate.  Set and adjust
them in S1_ptw_translate, and the various points at which we drop
secure state.  Initialize the space in get_phys_addr; for now leave
get_phys_addr_with_secure considering only secure vs non-secure spaces.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 26d19945944b4878fa84667487a5c4fe38df960a
      
https://github.com/qemu/qemu/commit/26d19945944b4878fa84667487a5c4fe38df960a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: NSTable is RES0 for the RME EL3 regime

Test in_space instead of in_secure so that we don't
switch out of Root space.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2f1ff4e7b9f30cc73e32bcb8e85fbe80a8925db1
      
https://github.com/qemu/qemu/commit/2f1ff4e7b9f30cc73e32bcb8e85fbe80a8925db1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Handle Block and Page bits for security space

With Realm security state, bit 55 of a block or page descriptor during
the stage2 walk becomes the NS bit; during the stage1 walk the bit 5
NS bit is RES0.  With Root security state, bit 11 of the block or page
descriptor during the stage1 walk becomes the NSE bit.

Rather than collecting an NS bit and applying it later, compute the
output pa space from the input pa space and unconditionally assign.
This means that we no longer need to adjust the output space earlier
for the NSTable bit.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4a7d7702cdfa776567535e55bdfb0a25f9c73d6f
      
https://github.com/qemu/qemu/commit/4a7d7702cdfa776567535e55bdfb0a25f9c73d6f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Handle no-execute for Realm and Root regimes

While Root and Realm may read and write data from other spaces,
neither may execute from other pa spaces.

This happens for Stage1 EL3, EL2, EL2&0, and Stage2 EL1&0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fe4a5472ccd62a6d10fa4b4f518a5dc707e62efd
      
https://github.com/qemu/qemu/commit/fe4a5472ccd62a6d10fa4b4f518a5dc707e62efd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Use get_phys_addr_with_struct in S1_ptw_translate

Do not provide a fast-path for physical addresses,
as those will need to be validated for GPC.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7c19b2d6d9c67910812da976c968500a1d6eb170
      
https://github.com/qemu/qemu/commit/7c19b2d6d9c67910812da976c968500a1d6eb170
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Move s1_is_el0 into S1Translate

Instead of passing this to get_phys_addr_lpae, stash it
in the S1Translate structure.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a5c7765202f3afcc1e0bf4ae87a89bffcfb50b33
      
https://github.com/qemu/qemu/commit/a5c7765202f3afcc1e0bf4ae87a89bffcfb50b33
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Use get_phys_addr_with_struct for stage2

This fixes a bug in which we failed to initialize
the result attributes properly after the memset.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f65a9bc7197a0cc7f4546631e3ad82945a36270f
      
https://github.com/qemu/qemu/commit/f65a9bc7197a0cc7f4546631e3ad82945a36270f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/syndrome.h

  Log Message:
  -----------
  target/arm: Add GPC syndrome

The function takes the fields as filled in by
the Arm ARM pseudocode for TakeGPCException.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 11b76fda0adcf84055863c42f8f6cebe3eef8ca0
      
https://github.com/qemu/qemu/commit/11b76fda0adcf84055863c42f8f6cebe3eef8ca0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/tcg/tlb_helper.c

  Log Message:
  -----------
  target/arm: Implement GPC exceptions

Handle GPC Fault types in arm_deliver_fault, reporting as
either a GPC exception at EL3, or falling through to insn
or data aborts at various exception levels.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 46f38c975f0a077a8f82081cc81a7cbd4f78f946
      
https://github.com/qemu/qemu/commit/46f38c975f0a077a8f82081cc81a7cbd4f78f946
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Implement the granule protection check

Place the check at the end of get_phys_addr_with_struct,
so that we check all physical results.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a834d5474e24a279ffc16558c34d4536e84fe09d
      
https://github.com/qemu/qemu/commit/a834d5474e24a279ffc16558c34d4536e84fe09d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Add cpu properties for enabling FEAT_RME

Add an x-rme cpu property to enable FEAT_RME.
Add an x-l0gptsz property to set GPCCR_EL3.L0GPTSZ,
for testing various possible configurations.

We're not currently completely sure whether FEAT_RME will
be OK to enable purely as a CPU-level property, or if it will
need board co-operation, so we're making these experimental
x- properties, so that the people developing the system
level software for RME can try to start using this and let
us know how it goes. The command line syntax for enabling
this will change in future, without backwards-compatibility.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-21-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 57223a4c24d58493d1eade8c1b38fd707f845d5e
      
https://github.com/qemu/qemu/commit/57223a4c24d58493d1eade8c1b38fd707f845d5e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M docs/system/arm/cpu-features.rst
    M docs/system/arm/emulation.rst

  Log Message:
  -----------
  docs/system/arm: Document FEAT_RME

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230622143046.1578160-1-richard.henderson@linaro.org
[PMM: fixed typo; note experimental status in emulation.rst too]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b0438861efe1dfbdfdd9fa1d9aa05100d37ea8ee
      
https://github.com/qemu/qemu/commit/b0438861efe1dfbdfdd9fa1d9aa05100d37ea8ee
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M include/qemu/compiler.h
    M include/qemu/host-utils.h

  Log Message:
  -----------
  host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang

We use __builtin_subcll() to do a 64-bit subtract with borrow-in and
borrow-out when the host compiler supports it.  Unfortunately some
versions of Apple Clang have a bug in their implementation of this
intrinsic which means it returns the wrong value.  The effect is that
a QEMU built with the affected compiler will hang when emulating x86
or m68k float80 division.

The upstream LLVM issue is:
https://github.com/llvm/llvm-project/issues/55253

The commit that introduced the bug apparently never made it into an
upstream LLVM release without the subsequent fix
https://github.com/llvm/llvm-project/commit/fffb6e6afdbaba563189c1f715058ed401fbc88d
but unfortunately it did make it into Apple Clang 14.0, as shipped
in Xcode 14.3 (14.2 is reported to be OK). The Apple bug number is
FB12210478.

Add ifdefs to avoid use of __builtin_subcll() on Apple Clang version
14 or greater.  There is not currently a version of Apple Clang which
has the bug fix -- when one appears we should be able to add an upper
bound to the ifdef condition so we can start using the builtin again.
We make the lower bound a conservative "any Apple clang with major
version 14 or greater" because the consequences of incorrectly
disabling the builtin when it would work are pretty small and the
consequences of not disabling it when we should are pretty bad.

Many thanks to those users who both reported this bug and also
did a lot of work in identifying the root cause; in particular
to Daniel Bertalan and osy.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1631
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1659
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Daniel Bertalan <dani@danielbertalan.dev>
Tested-by: Tested-By: Solra Bizna <solra@bizna.name>
Message-id: 20230622130823.1631719-1-peter.maydell@linaro.org


  Commit: 4315f7c6147431a69a02613fbdf9964d68f87a27
      
https://github.com/qemu/qemu/commit/4315f7c6147431a69a02613fbdf9964d68f87a27
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Restructure has_vfp_d32 test

One cannot test for feature aa32_simd_r32 without first
testing if AArch32 mode is supported at all.  This leads to

qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither

for Apple M1 cpus.

We already have a check for ARMv8-A never setting vfp-d32 true,
so restructure the code so that AArch64 avoids the test entirely.

Reported-by: Mads Ynddal <mads@ynddal.dk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mads Ynddal <m.ynddal@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Mads Ynddal <m.ynddal@samsung.com>
Message-id: 20230619140216.402530-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9fe2b4a2899507bc66122840f060fab74b5dd161
      
https://github.com/qemu/qemu/commit/9fe2b4a2899507bc66122840f060fab74b5dd161
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M docs/system/arm/sbsa.rst
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  hw/arm/sbsa-ref: add ITS support in SBSA GIC

Create ITS as part of SBSA platform GIC initialization.

GIC ITS information is in DeviceTree so TF-A can pass it to EDK2.

Bumping platform version to 0.2 as this is important hardware change.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20230619170913.517373-2-marcin.juszkiewicz@linaro.org
Co-authored-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7c347c7333d9c6651b0d0f985e7d919dc3aba607
      
https://github.com/qemu/qemu/commit/7c347c7333d9c6651b0d0f985e7d919dc3aba607
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Fix sve predicate store, 8 <= VQ <= 15

Brown bag time: store instead of load results in uninitialized temp.


Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1704
Reported-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620134659.817559-1-richard.henderson@linaro.org
Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, 
st}r")
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 497fad38979c16b6412388927401e577eba43d26
      
https://github.com/qemu/qemu/commit/497fad38979c16b6412388927401e577eba43d26
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M pc-bios/keymaps/meson.build

  Log Message:
  -----------
  pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy 
synonym

The xkb official name for the Arabic keyboard layout is 'ara'.
However xkb has for at least the past 15 years also permitted it to
be named via the legacy synonym 'ar'.  In xkeyboard-config 2.39 this
synoynm was removed, which breaks compilation of QEMU:

FAILED: pc-bios/keymaps/ar
/home/fred/qemu-git/src/qemu/build-full/qemu-keymap -f pc-bios/keymaps/ar -l ar
xkbcommon: ERROR: Couldn't find file "symbols/ar" in include paths
xkbcommon: ERROR: 1 include paths searched:
xkbcommon: ERROR:       /usr/share/X11/xkb
xkbcommon: ERROR: 3 include paths could not be added:
xkbcommon: ERROR:       /home/fred/.config/xkb
xkbcommon: ERROR:       /home/fred/.xkb
xkbcommon: ERROR:       /etc/xkb
xkbcommon: ERROR: Abandoning symbols file "(unnamed)"
xkbcommon: ERROR: Failed to compile xkb_symbols
xkbcommon: ERROR: Failed to compile keymap

The upstream xkeyboard-config change removing the compat
mapping is:
https://gitlab.freedesktop.org/xkeyboard-config/xkeyboard-config/-/commit/470ad2cd8fea84d7210377161d86b31999bb5ea6

Make QEMU always ask for the 'ara' xkb layout, which should work on
both older and newer xkeyboard-config.  We leave the QEMU name for
this keyboard layout as 'ar'; it is not the only one where our name
for it deviates from the xkb standard name.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20230620162024.1132013-1-peter.maydell@linaro.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1709


  Commit: 50ba97e928b44ff5bc731c9ffe68d86acbe44639
      
https://github.com/qemu/qemu/commit/50ba97e928b44ff5bc731c9ffe68d86acbe44639
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-06-24 (Sat, 24 Jun 2023)

  Changed paths:
    M hw/hppa/machine.c

  Log Message:
  -----------
  target/hppa: Fix OS reboot issues

When the OS triggers a reboot, the reset helper function sends a
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET) together with an
EXCP_HLT exception to halt the CPUs.

So, at reboot when initializing the CPUs again, make sure to set all
instruction pointers to the firmware entry point, disable any interrupts,
disable data and instruction translations, enable PSW_Q bit  and tell qemu
to unhalt (halted=0) the CPUs again.

This fixes the various reboot issues which were seen when rebooting a
Linux VM, including the case where even the monarch CPU has been virtually
halted from the OS (e.g. via "chcpu -d 0" inside the Linux VM).

Signed-off-by: Helge Deller <deller@gmx.de>


  Commit: 069d296669448b9eef72c6332ae84af962d9582c
      
https://github.com/qemu/qemu/commit/069d296669448b9eef72c6332ae84af962d9582c
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-06-24 (Sat, 24 Jun 2023)

  Changed paths:
    M hw/hppa/machine.c

  Log Message:
  -----------
  target/hppa: Provide qemu version via fw_cfg to firmware

Give current QEMU version string to SeaBIOS-hppa via fw_cfg interface so
that the firmware can show the QEMU version in the boot menu info.

Signed-off-by: Helge Deller <deller@gmx.de>


  Commit: 34ec3aea54368a92b62a55c656335885ba8c65ef
      
https://github.com/qemu/qemu/commit/34ec3aea54368a92b62a55c656335885ba8c65ef
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-06-24 (Sat, 24 Jun 2023)

  Changed paths:
    M pc-bios/hppa-firmware.img
    M roms/seabios-hppa

  Log Message:
  -----------
  target/hppa: Update to SeaBIOS-hppa version 8

Update SeaBIOS-hppa to version 8.

Fixes:
- boot of HP-UX with SMP, and
- reboot of Linux and HP-UX with SMP

Enhancements:
- show qemu version in boot menu
- adds exit menu entry in boot menu to quit emulation
- allow to trace PCD_CHASSIS codes & machine run status

Signed-off-by: Helge Deller <deller@gmx.de>


  Commit: fa7dd27bc3db5cc8a6224aeae6d368ab1553cda9
      
https://github.com/qemu/qemu/commit/fa7dd27bc3db5cc8a6224aeae6d368ab1553cda9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-25 (Sun, 25 Jun 2023)

  Changed paths:
    M docs/system/arm/cpu-features.rst
    M docs/system/arm/emulation.rst
    M docs/system/arm/sbsa.rst
    M hw/arm/sbsa-ref.c
    M include/exec/memattrs.h
    M include/qemu/compiler.h
    M include/qemu/host-utils.h
    M pc-bios/keymaps/meson.build
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/ptw.c
    M target/arm/syndrome.h
    M target/arm/tcg/cpu64.c
    M target/arm/tcg/tlb_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20230623' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Add (experimental) support for FEAT_RME
 * host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang
 * target/arm: Restructure has_vfp_d32 test
 * hw/arm/sbsa-ref: add ITS support in SBSA GIC
 * target/arm: Fix sve predicate store, 8 <= VQ <= 15
 * pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy 
synonym

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# =Q2Ei
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 23 Jun 2023 02:30:31 PM CEST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20230623' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (26 commits)
  pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy 
synonym
  target/arm: Fix sve predicate store, 8 <= VQ <= 15
  hw/arm/sbsa-ref: add ITS support in SBSA GIC
  target/arm: Restructure has_vfp_d32 test
  host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang
  docs/system/arm: Document FEAT_RME
  target/arm: Add cpu properties for enabling FEAT_RME
  target/arm: Implement the granule protection check
  target/arm: Implement GPC exceptions
  target/arm: Add GPC syndrome
  target/arm: Use get_phys_addr_with_struct for stage2
  target/arm: Move s1_is_el0 into S1Translate
  target/arm: Use get_phys_addr_with_struct in S1_ptw_translate
  target/arm: Handle no-execute for Realm and Root regimes
  target/arm: Handle Block and Page bits for security space
  target/arm: NSTable is RES0 for the RME EL3 regime
  target/arm: Pipe ARMSecuritySpace through ptw.c
  target/arm: Remove __attribute__((nonnull)) from ptw.c
  target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}
  target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 79dbd910c9ea6ca38f8e1b2616b1e5e885b85bd3
      
https://github.com/qemu/qemu/commit/79dbd910c9ea6ca38f8e1b2616b1e5e885b85bd3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-06-25 (Sun, 25 Jun 2023)

  Changed paths:
    M hw/hppa/machine.c
    M pc-bios/hppa-firmware.img
    M roms/seabios-hppa

  Log Message:
  -----------
  Merge tag 'hppa-boot-reboot-fixes-pull-request' of 
https://github.com/hdeller/qemu-hppa into staging

target/hppa: Fix boot and reboot for SMP machines

Fix some SMP-related boot and reboot issues with HP-UX and Linux by
correctly initializing the CPU PSW bits, disabling data and instruction
translations and unhalting the CPU in the qemu hppa_machine_reset()
function.

To work correctly some fixes are needed in the SeaBIOS-hppa firmware too,
which is why this series updates it to version 8 which includes those
fixes and enhancements:

Fixes
- boot of HP-UX with SMP, and
- reboot of Linux and HP-UX with SMP

Enhancements:
- show qemu version in boot menu
- adds exit menu entry in boot menu to quit emulation
- allow to trace PCD_CHASSIS codes more specifically

Signed-off-by: Helge Deller <deller@gmx.de>

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# =8zCK
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# gpg: Signature made Sat 24 Jun 2023 01:49:44 PM CEST
# gpg:                using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg:                 aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D  25F8 3E5F 3D04 A7A2 4603
#      Subkey fingerprint: BCE9 123E 1AD2 9F07 C049  BBDE F712 B510 A23A 0F5F

* tag 'hppa-boot-reboot-fixes-pull-request' of 
https://github.com/hdeller/qemu-hppa:
  target/hppa: Update to SeaBIOS-hppa version 8
  target/hppa: Provide qemu version via fw_cfg to firmware
  target/hppa: Fix OS reboot issues

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/d198dab7131d...79dbd910c9ea