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[Qemu-commits] [qemu/qemu] 732d54: accel: Replace target_ulong in tlb_*(
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 732d54: accel: Replace target_ulong in tlb_*() |
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Date: |
Mon, 26 Jun 2023 08:41:22 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 732d548732edda90f3cfe0f7dceee64861f07b25
https://github.com/qemu/qemu/commit/732d548732edda90f3cfe0f7dceee64861f07b25
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/stubs/tcg-stub.c
M accel/tcg/cputlb.c
M accel/tcg/tb-maint.c
M include/exec/cpu-defs.h
M include/exec/exec-all.h
M include/qemu/plugin-memory.h
Log Message:
-----------
accel: Replace target_ulong in tlb_*()
Replaces target_ulong with vaddr for guest virtual addresses in tlb_*()
functions and auxilliary structs.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-2-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 256d11f9ba23c74db75d50b24e3357d583d7885b
https://github.com/qemu/qemu/commit/256d11f9ba23c74db75d50b24e3357d583d7885b
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/internal.h
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg/translate-all.c: Widen pc and cs_base
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-3-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: bb5de52524c6c4b7da5623c5b19d9d6dc8405aa0
https://github.com/qemu/qemu/commit/bb5de52524c6c4b7da5623c5b19d9d6dc8405aa0
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/translate-all.c
M target/alpha/cpu.h
M target/arm/cpu.h
M target/arm/helper.c
M target/avr/cpu.h
M target/cris/cpu.h
M target/hexagon/cpu.h
M target/hppa/cpu.h
M target/i386/cpu.h
M target/loongarch/cpu.h
M target/m68k/cpu.h
M target/microblaze/cpu.h
M target/mips/cpu.h
M target/nios2/cpu.h
M target/openrisc/cpu.h
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/rx/cpu.h
M target/s390x/cpu.h
M target/sh4/cpu.h
M target/sparc/cpu.h
M target/tricore/cpu.h
M target/xtensa/cpu.h
Log Message:
-----------
target: Widen pc/cs_base in cpu_get_tb_cpu_state
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-4-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9e39de980fdf0dbb083a5c78b71bf2c1bdfa0499
https://github.com/qemu/qemu/commit/9e39de980fdf0dbb083a5c78b71bf2c1bdfa0499
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/cpu_ldst.h
Log Message:
-----------
accel/tcg/cputlb.c: Widen CPUTLBEntry access functions
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-5-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fb2c53cb710e3f3a4c6d4bb6f2465295e216b835
https://github.com/qemu/qemu/commit/fb2c53cb710e3f3a4c6d4bb6f2465295e216b835
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg/cputlb.c: Widen addr in MMULookupPageData
Functions accessing MMULookupPageData are also updated.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-6-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f0a08b0913befbd400c16fb444612b6d034a2c53
https://github.com/qemu/qemu/commit/f0a08b0913befbd400c16fb444612b6d034a2c53
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg/cpu-exec.c: Widen pc to vaddr
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-7-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 06f3831c08ac0d36ce3d0b1f2deaa8ec1e1d8d7e
https://github.com/qemu/qemu/commit/06f3831c08ac0d36ce3d0b1f2deaa8ec1e1d8d7e
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/tb-hash.h
M accel/tcg/tb-jmp-cache.h
Log Message:
-----------
accel/tcg: Widen pc to vaddr in CPUJumpCache
Related functions dealing with the jump cache are also updated.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-8-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4f8f41272eec57105e82dbb5761354ef0da9f7b0
https://github.com/qemu/qemu/commit/4f8f41272eec57105e82dbb5761354ef0da9f7b0
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/stubs/tcg-stub.c
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M include/exec/exec-all.h
Log Message:
-----------
accel: Replace target_ulong with vaddr in probe_*()
Functions for probing memory accesses (and functions that call these)
are updated to take a vaddr for guest virtual addresses over
target_ulong.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-9-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b0326eb99917d99a37c8cd9d479a2e9b04659076
https://github.com/qemu/qemu/commit/b0326eb99917d99a37c8cd9d479a2e9b04659076
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg: Replace target_ulong with vaddr in *_mmu_lookup()
Update atomic_mmu_lookup() and cpu_mmu_lookup() to take the guest
virtual address as a vaddr instead of a target_ulong.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-10-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b1c09220b4cef17632495bfbb9a1355ce3eb301c
https://github.com/qemu/qemu/commit/b1c09220b4cef17632495bfbb9a1355ce3eb301c
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/translator.c
M include/exec/translator.h
Log Message:
-----------
accel/tcg: Replace target_ulong with vaddr in translator_*()
Use vaddr for guest virtual address in translator_use_goto_tb() and
translator_loop().
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-11-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c814c892e5e7f55eb5184e4aaf3bfa918070fbb1
https://github.com/qemu/qemu/commit/c814c892e5e7f55eb5184e4aaf3bfa918070fbb1
Author: Anton Johansson <anjo@rev.ng>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M cpu.c
M include/exec/exec-all.h
Log Message:
-----------
cpu: Replace target_ulong with hwaddr in tb_invalidate_phys_addr()
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-13-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1d3daf95254d998b91445c48de875796df3b0998
https://github.com/qemu/qemu/commit/1d3daf95254d998b91445c48de875796df3b0998
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining
Balton discovered that asserts for the extract/deposit calls had a
significant impact on a lame benchmark on qemu-ppc. Replicating with:
./qemu-ppc64 ~/lsrc/tests/lame.git-svn/builds/ppc64/frontend/lame \
-h pts-trondheim-3.wav pts-trondheim-3.mp3
showed up the pack/unpack routines not eliding the assert checks as it
should have done causing them to prominently figure in the profile:
11.44% qemu-ppc64 qemu-ppc64 [.] unpack_raw64.isra.0
11.03% qemu-ppc64 qemu-ppc64 [.] parts64_uncanon_normal
8.26% qemu-ppc64 qemu-ppc64 [.] helper_compute_fprf_float64
6.75% qemu-ppc64 qemu-ppc64 [.] do_float_check_status
5.34% qemu-ppc64 qemu-ppc64 [.] parts64_muladd
4.75% qemu-ppc64 qemu-ppc64 [.] pack_raw64.isra.0
4.38% qemu-ppc64 qemu-ppc64 [.] parts64_canonicalize
3.62% qemu-ppc64 qemu-ppc64 [.]
float64r32_round_pack_canonical
After this patch the same test runs 31 seconds faster with a profile
where the generated code dominates more:
+ 14.12% 0.00% qemu-ppc64 [unknown] [.]
0x0000004000619420
+ 13.30% 0.00% qemu-ppc64 [unknown] [.]
0x0000004000616850
+ 12.58% 12.19% qemu-ppc64 qemu-ppc64 [.]
parts64_uncanon_normal
+ 10.62% 0.00% qemu-ppc64 [unknown] [.]
0x000000400061bf70
+ 9.91% 9.73% qemu-ppc64 qemu-ppc64 [.]
helper_compute_fprf_float64
+ 7.84% 7.82% qemu-ppc64 qemu-ppc64 [.]
do_float_check_status
+ 6.47% 5.78% qemu-ppc64 qemu-ppc64 [.]
parts64_canonicalize.constprop.0
+ 6.46% 0.00% qemu-ppc64 [unknown] [.]
0x0000004000620130
+ 6.42% 0.00% qemu-ppc64 [unknown] [.]
0x0000004000619400
+ 6.17% 6.04% qemu-ppc64 qemu-ppc64 [.] parts64_muladd
+ 5.85% 0.00% qemu-ppc64 [unknown] [.]
0x00000040006167e0
+ 5.74% 0.00% qemu-ppc64 [unknown] [.]
0x0000b693fcffffd3
+ 5.45% 4.78% qemu-ppc64 qemu-ppc64 [.]
float64r32_round_pack_canonical
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <ec9cfe5a-d5f2-466d-34dc-c35817e7e010@linaro.org>
[AJB: Patchified rth's suggestion]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20230523131107.3680641-1-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ea185a557bc97868f3729060ea1cd003dbd971d1
https://github.com/qemu/qemu/commit/ea185a557bc97868f3729060ea1cd003dbd971d1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M tests/plugin/insn.c
M tests/tcg/i386/Makefile.softmmu-target
M tests/tcg/i386/Makefile.target
M tests/tcg/x86_64/Makefile.softmmu-target
Log Message:
-----------
tests/plugin: Remove duplicate insn log from libinsn.so
This is a perfectly natural occurrence for x86 "rep movb",
where the "rep" prefix forms a counted loop of the one insn.
During the tests/tcg/multiarch/memory test, this logging is
triggered over 350000 times. Within the context of cross-i386-tci
build, which is already slow by nature, the logging is sufficient
to push the test into timeout.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1b65b4f54c7f7d07b5d35fac5f7de3e75f5f21a0
https://github.com/qemu/qemu/commit/1b65b4f54c7f7d07b5d35fac5f7de3e75f5f21a0
Author: Fei Wu <fei2.wu@intel.com>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/monitor.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/translate-all.c
M hmp-commands-info.hx
M include/qemu/timer.h
M include/tcg/tcg.h
M meson.build
M meson_options.txt
M qapi/machine.json
M scripts/meson-buildoptions.sh
M softmmu/runstate.c
M tcg/tcg.c
M tests/qtest/qmp-cmd-test.c
Log Message:
-----------
accel/tcg: remove CONFIG_PROFILER
TBStats will be introduced to replace CONFIG_PROFILER totally, here
remove all CONFIG_PROFILER related stuffs first.
Signed-off-by: Vanderson M. do Rosario <vandersonmr2@gmail.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Fei Wu <fei2.wu@intel.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230607122411.3394702-2-fei2.wu@intel.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 70bfde9a7de7fa3495d9e2bd7142cb1bc656484e
https://github.com/qemu/qemu/commit/70bfde9a7de7fa3495d9e2bd7142cb1bc656484e
Author: Max Chou <max.chou@sifive.com>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Fix temporary variable in tcg_gen_gvec_andcs
The 5th parameter of tcg_gen_gvec_2s should be replaced by the
temporary tmp variable in the tcg_gen_gvec_andcs function.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-Id: <20230622161646.32005-9-max.chou@sifive.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f6ff4923b92ceefbe5650c3e90ccdcc57dc60fb7
https://github.com/qemu/qemu/commit/f6ff4923b92ceefbe5650c3e90ccdcc57dc60fb7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M target/microblaze/cpu.h
Log Message:
-----------
target/microblaze: Define TCG_GUEST_DEFAULT_MO
The microblaze architecture does not reorder instructions.
While there is an MBAR wait-for-data-access instruction,
this concerns synchronizing with DMA.
This should have been defined when enabling MTTCG.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Fixes: d449561b130 ("configure: microblaze: Enable mttcg")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c914d46d0a645e7c633292146f4e38c945d4f847
https://github.com/qemu/qemu/commit/c914d46d0a645e7c633292146f4e38c945d4f847
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Do not elide memory barriers for !CF_PARALLEL in system mode
The virtio devices require proper memory ordering between
the vcpus and the iothreads.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f86e8f3d138de112d66ec28792e0fd303bf129ca
https://github.com/qemu/qemu/commit/f86e8f3d138de112d66ec28792e0fd303bf129ca
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/internal.h
M accel/tcg/user-exec.c
Log Message:
-----------
tcg: Add host memory barriers to cpu_ldst.h interfaces
Bring the helpers into line with the rest of tcg in respecting
guest memory ordering.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 97e1576957c28a5fbcc810f92643e52069cc49b7
https://github.com/qemu/qemu/commit/97e1576957c28a5fbcc810f92643e52069cc49b7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/tcg-all.c
Log Message:
-----------
accel/tcg: Remove check_tcg_memory_orders_compatible
We now issue host memory barriers to match the guest memory order.
Continue to disable MTTCG only if the guest has not been ported.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 58e8f1f616d117aed6283690419dc16f53b7a202
https://github.com/qemu/qemu/commit/58e8f1f616d117aed6283690419dc16f53b7a202
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/cpu-all.h
M include/exec/cpu-defs.h
M include/hw/core/cpu.h
Log Message:
-----------
accel/tcg: Store some tlb flags in CPUTLBEntryFull
We have run out of bits we can use within the CPUTLBEntry comparators,
as TLB_FLAGS_MASK cannot overlap alignment.
Store slow_flags[] in CPUTLBEntryFull, and merge with the flags from
the comparator. A new TLB_FORCE_SLOW bit is set within the comparator
as an indication that the slow path must be used.
Move TLB_BSWAP to TLB_SLOW_FLAGS_MASK. Since we are out of bits,
we cannot create a new bit without moving an old one.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 187ba6945345cedf2f343fcc33e5616186aebe9d
https://github.com/qemu/qemu/commit/187ba6945345cedf2f343fcc33e5616186aebe9d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/cpu-all.h
Log Message:
-----------
accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK
This frees up one bit of the primary tlb flags without
impacting the TLB_NOTDIRTY logic.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a0eaae08c7c6a59c185cf646b02f4167b2ac6ec0
https://github.com/qemu/qemu/commit/a0eaae08c7c6a59c185cf646b02f4167b2ac6ec0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M include/exec/cpu-all.h
M tcg/tcg-op-ldst.c
Log Message:
-----------
accel/tcg: Renumber TLB_DISCARD_WRITE
Move to fill a hole in the set of bits.
Reduce the total number of tlb bits by 1.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4329d049d5b8d4af71c6b399d64a6d1b98856318
https://github.com/qemu/qemu/commit/4329d049d5b8d4af71c6b399d64a6d1b98856318
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M accel/stubs/tcg-stub.c
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/internal.h
M accel/tcg/monitor.c
M accel/tcg/tb-hash.h
M accel/tcg/tb-jmp-cache.h
M accel/tcg/tb-maint.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/tcg-all.c
M accel/tcg/translate-all.c
M accel/tcg/translator.c
M accel/tcg/user-exec.c
M cpu.c
M fpu/softfloat.c
M hmp-commands-info.hx
M include/exec/cpu-all.h
M include/exec/cpu-defs.h
M include/exec/cpu_ldst.h
M include/exec/exec-all.h
M include/exec/translator.h
M include/hw/core/cpu.h
M include/qemu/plugin-memory.h
M include/qemu/timer.h
M include/tcg/tcg.h
M meson.build
M meson_options.txt
M qapi/machine.json
M scripts/meson-buildoptions.sh
M softmmu/runstate.c
M target/alpha/cpu.h
M target/arm/cpu.h
M target/arm/helper.c
M target/avr/cpu.h
M target/cris/cpu.h
M target/hexagon/cpu.h
M target/hppa/cpu.h
M target/i386/cpu.h
M target/loongarch/cpu.h
M target/m68k/cpu.h
M target/microblaze/cpu.h
M target/mips/cpu.h
M target/nios2/cpu.h
M target/openrisc/cpu.h
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/rx/cpu.h
M target/s390x/cpu.h
M target/sh4/cpu.h
M target/sparc/cpu.h
M target/tricore/cpu.h
M target/xtensa/cpu.h
M tcg/tcg-op-gvec.c
M tcg/tcg-op-ldst.c
M tcg/tcg-op.c
M tcg/tcg.c
M tests/plugin/insn.c
M tests/qtest/qmp-cmd-test.c
M tests/tcg/i386/Makefile.softmmu-target
M tests/tcg/i386/Makefile.target
M tests/tcg/x86_64/Makefile.softmmu-target
Log Message:
-----------
Merge tag 'pull-tcg-20230626' of https://gitlab.com/rth7680/qemu into staging
accel/tcg: Replace target_ulong in some APIs
accel/tcg: Remove CONFIG_PROFILER
accel/tcg: Store some tlb flags in CPUTLBEntryFull
tcg: Issue memory barriers as required for the guest memory model
tcg: Fix temporary variable in tcg_gen_gvec_andcs
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# gpg: Signature made Mon 26 Jun 2023 05:38:32 PM CEST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[ultimate]
* tag 'pull-tcg-20230626' of https://gitlab.com/rth7680/qemu: (22 commits)
accel/tcg: Renumber TLB_DISCARD_WRITE
accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK
accel/tcg: Store some tlb flags in CPUTLBEntryFull
accel/tcg: Remove check_tcg_memory_orders_compatible
tcg: Add host memory barriers to cpu_ldst.h interfaces
tcg: Do not elide memory barriers for !CF_PARALLEL in system mode
target/microblaze: Define TCG_GUEST_DEFAULT_MO
tcg: Fix temporary variable in tcg_gen_gvec_andcs
accel/tcg: remove CONFIG_PROFILER
tests/plugin: Remove duplicate insn log from libinsn.so
softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining
cpu: Replace target_ulong with hwaddr in tb_invalidate_phys_addr()
accel/tcg: Replace target_ulong with vaddr in translator_*()
accel/tcg: Replace target_ulong with vaddr in *_mmu_lookup()
accel: Replace target_ulong with vaddr in probe_*()
accel/tcg: Widen pc to vaddr in CPUJumpCache
accel/tcg/cpu-exec.c: Widen pc to vaddr
accel/tcg/cputlb.c: Widen addr in MMULookupPageData
accel/tcg/cputlb.c: Widen CPUTLBEntry access functions
target: Widen pc/cs_base in cpu_get_tb_cpu_state
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/390e8fc6b0e7...4329d049d5b8
- [Qemu-commits] [qemu/qemu] 732d54: accel: Replace target_ulong in tlb_*(),
Richard Henderson <=