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[Qemu-commits] [qemu/qemu] 67f853: icount: don't adjust virtual time bac
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 67f853: icount: don't adjust virtual time backwards after ... |
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Date: |
Thu, 29 Jun 2023 05:55:42 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 67f85346ca9305d9fb3254ceff735ceaadeb0911
https://github.com/qemu/qemu/commit/67f85346ca9305d9fb3254ceff735ceaadeb0911
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-06-27 (Tue, 27 Jun 2023)
Changed paths:
M softmmu/icount.c
Log Message:
-----------
icount: don't adjust virtual time backwards after warp
The icount-based QEMU_CLOCK_VIRTUAL runs ahead of the RT clock at times.
When warping, it is possible it is still ahead at the end of the warp,
which causes icount adaptive mode to adjust it backward. This can result
in the machine observing time going backwards.
Prevent this by clamping adaptive adjustment to 0 at minimum.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230627061406.241847-1-npiggin@gmail.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5bef742cc4f0e21c80a31611af7881ba811e507f
https://github.com/qemu/qemu/commit/5bef742cc4f0e21c80a31611af7881ba811e507f
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: 2023-06-29 (Thu, 29 Jun 2023)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Export MSR_ARCH_CAPABILITIES bits to guests
On Intel CPUs there are certain bits in MSR_ARCH_CAPABILITIES that
indicates if the CPU is not affected by a vulnerability. Without these
bits guests may try to deploy the mitigation even if the CPU is not
affected.
Export the bits to guests that indicate immunity to hardware
vulnerabilities.
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Message-ID:
<63d85cc76d4cdc51e6c732478b81d8f13be11e5a.1687551881.git.pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9fb4f5f5a1fd7619e221fd5068003c5b491b2bf0
https://github.com/qemu/qemu/commit/9fb4f5f5a1fd7619e221fd5068003c5b491b2bf0
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-06-29 (Thu, 29 Jun 2023)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: ignore ARCH_CAPABILITIES features in user mode emulation
ARCH_CAPABILITIES is only accessible through a read-only MSR, so it has
no impact on any user-mode operation (user-mode cannot read the MSR).
So do not bother printing warnings about it in user mode emulation.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d903259dd2dbe40e007db1724dd072c5e210b3f4
https://github.com/qemu/qemu/commit/d903259dd2dbe40e007db1724dd072c5e210b3f4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-06-29 (Thu, 29 Jun 2023)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: ignore CPL0-specific features in user mode emulation
Features such as PCID are only accessible through privileged operations,
and therefore have no impact on any user-mode operation. Allow reporting
them to programs running under user mode emulation, so that "-cpu" can be
used with more named CPU models.
XSAVES would be similar, but it doesn't make sense to provide it until
XSAVEC is implemented.
With this change, all CPUs up to Broadwell-v4 can be emulate. Skylake-Client
requires XSAVEC, while EPYC also requires SHA-NI, MISALIGNSSE and TOPOEXT.
MISALIGNSSE is not hard to implement, but I am not sure it is worth using
a precious hflags bit for it.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1534
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 40a205da415e9c10ff02505078700e14ead77092
https://github.com/qemu/qemu/commit/40a205da415e9c10ff02505078700e14ead77092
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-06-29 (Thu, 29 Jun 2023)
Changed paths:
M linux-user/i386/cpu_loop.c
M target/i386/cpu.c
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: emulate 64-bit ring 0 for linux-user if LM feature is set
32-bit binaries can run on a long mode processor even if the kernel
is 64-bit, of course, and this can have slightly different behavior;
for example, SYSCALL is allowed on Intel processors.
Allow reporting LM to programs running under user mode emulation,
so that "-cpu" can be used with named CPU models even for qemu-i386
and even without disabling LM by hand.
Fortunately, most of the runtime code in QEMU has to depend on HF_LMA_MASK
or on HF_CS64_MASK (which is anyway false for qemu-i386's 32-bit code
segment) rather than TARGET_X86_64, therefore all that is needed is an
update of linux-user's ring 0 setup.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1534
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4d541f63e90c81112c298cbb35ed53e9c79deb00
https://github.com/qemu/qemu/commit/4d541f63e90c81112c298cbb35ed53e9c79deb00
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-06-29 (Thu, 29 Jun 2023)
Changed paths:
M linux-user/i386/cpu_loop.c
M softmmu/icount.c
M target/i386/cpu.c
M target/i386/tcg/translate.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* Make named CPU models usable for qemu-{i386,x86_64}
* Fix backwards time with -icount auto
# -----BEGIN PGP SIGNATURE-----
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# =oj3B
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 29 Jun 2023 10:51:48 AM CEST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
target/i386: emulate 64-bit ring 0 for linux-user if LM feature is set
target/i386: ignore CPL0-specific features in user mode emulation
target/i386: ignore ARCH_CAPABILITIES features in user mode emulation
target/i386: Export MSR_ARCH_CAPABILITIES bits to guests
icount: don't adjust virtual time backwards after warp
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/017b2e736362...4d541f63e90c