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[Qemu-commits] [qemu/qemu] b5ea67: pnv/psi: Allow access to PSI register
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] b5ea67: pnv/psi: Allow access to PSI registers through xscom |
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Date: |
Fri, 07 Jul 2023 23:23:09 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: b5ea6754e8f913c82197dc26973d7d7ee4aef91f
https://github.com/qemu/qemu/commit/b5ea6754e8f913c82197dc26973d7d7ee4aef91f
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv_psi.c
Log Message:
-----------
pnv/psi: Allow access to PSI registers through xscom
skiboot only uses mmio to access the PSI registers (once the BAR is
set) but we don't have any reason to block the accesses through
xscom. This patch enables xscom access to the PSI registers. It
converts the xscom addresses to mmio addresses, which requires a bit
of care for the PSIHB, then reuse the existing mmio ops.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230630102609.193214-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a5ff7875a9e50180c354471f931f863a26283ce1
https://github.com/qemu/qemu/commit/a5ff7875a9e50180c354471f931f863a26283ce1
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc.c
Log Message:
-----------
target/ppc: Make HDECR underflow edge triggered
HDEC interrupts are edge-triggered on HDECR underflow (notably different
from DEC which is level-triggered).
HDEC interrupts already clear the irq on delivery so that does not need
to be changed.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230625122045.15544-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2ad2e113deb5663e69a05dd6922cbfc6d7ea34d3
https://github.com/qemu/qemu/commit/2ad2e113deb5663e69a05dd6922cbfc6d7ea34d3
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc.c
Log Message:
-----------
hw/ppc: Fix clock update drift
The clock update logic reads the clock twice to compute the new clock
value, with a value derived from the later time subtracted from a value
derived from the earlier time. The delta causes time to be lost.
This can ultimately result in time becoming unsynchronized between CPUs
and that can cause OS lockups, timeouts, watchdogs, etc. This can be
seen running a KVM guest (that causes lots of TB updates) on a powernv
SMP machine.
Fix this by reading the clock once.
Cc: qemu-stable@nongnu.org
Fixes: dbdd25065e90 ("Implement time-base start/stop helpers.")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-ID: <20230629020713.327745-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 28eafc1270c5878a2f2538b8050443f88c5c9282
https://github.com/qemu/qemu/commit/28eafc1270c5878a2f2538b8050443f88c5c9282
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/meson.build
Log Message:
-----------
target/ppc: Only generate decodetree files when TCG is enabled
No need to generate TCG-specific decodetree files
when TCG is disabled.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230626140100.67941-1-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 32be62a3d811fa9f389ff791ac6c5cecf69b2109
https://github.com/qemu/qemu/commit/32be62a3d811fa9f389ff791ac6c5cecf69b2109
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/pci-host/mv64361.c
M hw/pci-host/mv643xx.h
Log Message:
-----------
mv64361: Add dummy gigabit ethernet PHY access registers
We don't emulate the gigabit ethernet part of the chip but the MorphOS
driver accesses these and expects to get some valid looking result
otherwise it hangs. Add some minimal dummy implementation to avoid rhis.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230605215145.29458746335@zero.eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6f967f4f7869cd393585946ed43427c626a15d40
https://github.com/qemu/qemu/commit/6f967f4f7869cd393585946ed43427c626a15d40
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Tidy POWER book4 SPR registration
POWER book4 (implementation-specific) SPRs are sometimes in their own
functions, but in other cases are mixed with architected SPRs. Do some
spring cleaning on these.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230625120317.13877-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b25f2ffa19c0f4a79de0315d4eade36ce76b031c
https://github.com/qemu/qemu/commit/b25f2ffa19c0f4a79de0315d4eade36ce76b031c
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/spr_common.h
M target/ppc/timebase_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add TFMR SPR implementation with read and write helpers
TFMR is the Time Facility Management Register which is specific to
POWER CPUs, and used for the purpose of timebase management (generally
by firmware, not the OS).
Add helpers for the TFMR register, which will form part of the core
timebase facility model in future but for now behaviour is unchanged.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230625120317.13877-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: bc65beb3a412b3d6d7e16d9f11a9712a086aae02
https://github.com/qemu/qemu/commit/bc65beb3a412b3d6d7e16d9f11a9712a086aae02
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/net/sungem.c
M hw/net/trace-events
Log Message:
-----------
sungem: Add WOL MMIO
Apple sungem devices are expected to have WOL MMIO registers.
Add a region to prevent transaction failures, and implement the
WOL-disable CSR write because the Linux driver reset writes
this.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-ID: <20230625201628.65231-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c32654af150191e376d2d89dba4afbb31c8e9958
https://github.com/qemu/qemu/commit/c32654af150191e376d2d89dba4afbb31c8e9958
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Fix icount access for some hypervisor instructions
Several instructions and register access require icount reads and are
missing translator_io_start().
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230625103700.8992-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: d2b4e29768d783a85a3756bf349ca33f63688ba1
https://github.com/qemu/qemu/commit/d2b4e29768d783a85a3756bf349ca33f63688ba1
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M tests/avocado/replay_kernel.py
Log Message:
-----------
tests/avocado: record_replay test for ppc powernv machine
The powernv machine can boot Linux to VFS mount with icount enabled.
Add a test case for it.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230625103700.8992-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: d73a17515035a006eb09272b8d554833e11140bb
https://github.com/qemu/qemu/commit/d73a17515035a006eb09272b8d554833e11140bb
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Allow indirect TIMA accesses of all sizes
Booting linux on the powernv10 machine logs a few errors like:
Invalid read at addr 0x38, size 1, region 'xive-ic-tm-indirect', reason:
invalid size (min:8 max:8)
Invalid write at addr 0x38, size 1, region 'xive-ic-tm-indirect', reason:
invalid size (min:8 max:8)
Invalid read at addr 0x38, size 1, region 'xive-ic-tm-indirect', reason:
invalid size (min:8 max:8)
Those errors happen when linux is resetting XIVE. We're trying to
read/write the enablement bit for the hardware context and qemu
doesn't allow indirect TIMA accesses of less than 8 bytes. Direct TIMA
access can go through though, as well as indirect TIMA accesses on P9.
So even though there are some restrictions regarding the address/size
combinations for TIMA access, the example above is perfectly valid.
This patch lets indirect TIMA accesses of all sizes go through. The
special operations will be intercepted and the default "raw" handlers
will pick up all other requests and complain about invalid sizes as
appropriate.
Tested-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230626094057.1192473-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2306c60633f8f2811e5f42666b8155a8d2065154
https://github.com/qemu/qemu/commit/2306c60633f8f2811e5f42666b8155a8d2065154
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove some superfluous parentheses
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID:
<8384ed0f7335093012bbd3d28fb2a543a2e7346c.1686868895.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 3f88a89d10b2391a6cce1d3e1c77bafc586f215d
https://github.com/qemu/qemu/commit/3f88a89d10b2391a6cce1d3e1c77bafc586f215d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove unneeded parameter from powerpc_reset_wakeup()
CPUState is rarely needed by this function (only for logging a fatal
error) and it's easy to get from the env parameter so passing it
separately is not necessary.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID:
<f42761401c708fd6e02f7523d9f709b1972e5863.1686868895.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 819b31b0b43813a32c91bebf8c8dce82a9bff389
https://github.com/qemu/qemu/commit/819b31b0b43813a32c91bebf8c8dce82a9bff389
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Move common check in exception handlers to a function
All powerpc exception handlers share some code when handling machine
check exceptions. Move this to a common function.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID:
<9cfffaa35aa894086dd092af6b0b26f2d62ff3de.1686868895.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0661329a356c17bb1fabef99a45b21b52a43fb08
https://github.com/qemu/qemu/commit/0661329a356c17bb1fabef99a45b21b52a43fb08
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove some more local CPUState variables only used once
Some helpers only have a CPUState local to call cpu_interrupt_exittb()
but we can use env_cpu for that and remove the local.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID:
<aa34e449552c6ab52d48938ccbe762fc06adac01.1686868895.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 08d7cfd04c3e90b0e904918cd785352e50bc17e1
https://github.com/qemu/qemu/commit/08d7cfd04c3e90b0e904918cd785352e50bc17e1
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppd: Remove unused define
Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop
the unused define as well.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID:
<50adc24f9d408882128e896d8a81a1a059c41836.1686868895.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 4e6b7db2c3331ccc2cae24443950a501181a9a0c
https://github.com/qemu/qemu/commit/4e6b7db2c3331ccc2cae24443950a501181a9a0c
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Get CPUState in one step
We can get CPUState from env with env_cpu without going through
PowerPCCPU and casting that.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID:
<28424220f37f51ce97f24cadc7538a9c0d16cb45.1686868895.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 93c691a003193a8bc4db54f4e544e19d6b1016fc
https://github.com/qemu/qemu/commit/93c691a003193a8bc4db54f4e544e19d6b1016fc
Author: Narayana Murty N <nnmlinux@linux.ibm.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/arch_dump.c
Log Message:
-----------
target: ppc: Use MSR_HVB bit to get the target endianness for memory dump
Currently on PPC64 qemu always dumps the guest memory in
Big Endian (BE) format even though the guest running in Little Endian
(LE) mode. So crash tool fails to load the dump as illustrated below:
Log :
$ virsh dump DOMAIN --memory-only dump.file
Domain 'DOMAIN' dumped to dump.file
$ crash vmlinux dump.file
<snip>
crash 8.0.2-1.el9
WARNING: endian mismatch:
crash utility: little-endian
dump.file: big-endian
WARNING: machine type mismatch:
crash utility: PPC64
dump.file: (unknown)
crash: dump.file: not a supported file format
<snip>
This happens because cpu_get_dump_info() passes cpu->env->has_hv_mode
to function ppc_interrupts_little_endian(), the cpu->env->has_hv_mode
always set for powerNV even though the guest is not running in hv mode.
The hv mode should be taken from msr_mask MSR_HVB bit
(cpu->env.msr_mask & MSR_HVB). This patch fixes the issue by passing
MSR_HVB value to ppc_interrupts_little_endian() in order to determine
the guest endianness.
The crash tool also expects guest kernel endianness should match the
endianness of the dump.
The patch was tested on POWER9 box booted with Linux as host in
following cases:
Host-Endianess Qemu-Target-Machine Qemu-Generated-Guest
Memory-Dump-Format
BE powernv(OPAL/PowerNV) LE
BE powernv(OPAL/PowerNV) BE
LE powernv(OPAL/PowerNV) LE
LE powernv(OPAL/PowerNV) BE
LE pseries(OPAL/PowerNV/pSeries) KVMHV LE
LE pseries TCG LE
Fixes: 5609400a4228 ("target/ppc: Set the correct endianness for powernv memory
dumps")
Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Vaibhav Jain <vaibhav@linux.ibm.com>
Message-ID: <20230623072506.34713-1-nnmlinux@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 694d3cb2ef2d7355ddaf413614f325f17da9716b
https://github.com/qemu/qemu/commit/694d3cb2ef2d7355ddaf413614f325f17da9716b
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Fix TIMA offset for indirect access
Direct TIMA operations can be done through 4 pages, each with a
different privilege level dictating what fields can be accessed. On
the other hand, indirect TIMA accesses on P10 are done through a
single page, which is the equivalent of the most privileged page of
direct TIMA accesses.
The offset in the IC bar of an indirect access specifies what hw
thread is targeted (page shift bits) and the offset in the
TIMA being accessed (the page offset bits). When the indirect
access is calling the underlying direct access functions, it is
therefore important to clearly separate the 2, as the direct functions
assume any page shift bits define the privilege ring level. For
indirect accesses, those bits must be 0. This patch fixes the offset
passed to direct TIMA functions.
It didn't matter for SMT1, as the 2 least significant bits of the page
shift are part of the hw thread ID and always 0, so the direct TIMA
functions were accessing the privilege ring 0 page. With SMT4/8, it is
no longer true.
The fix is specific to P10, as indirect TIMA access on P9 was handled
differently.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230703080858.54060-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a8da2e1424c2f716222582a4706117d2ca845fe1
https://github.com/qemu/qemu/commit/a8da2e1424c2f716222582a4706117d2ca845fe1
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
pnv/xive: Add property on xive sources to define PQ state on reset
The PQ state of a xive interrupt is always initialized to Q=1, which
means the interrupt is disabled. Since a xive source can be embedded
in many objects, this patch adds a property to allow that behavior to
be refined if needed.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230703081215.55252-2-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 4a1e9449e8d55c173f3eddd94ae363c2c2938fda
https://github.com/qemu/qemu/commit/4a1e9449e8d55c173f3eddd94ae363c2c2938fda
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv_psi.c
Log Message:
-----------
pnv/psi: Initialize the PSIHB interrupts to match hardware
On the powernv9 and powernv10 machines, the PSIHB interrupts are
currently initialized with a PQ state of 0b01, i.e. interrupts are
disabled. However real hardware initializes them to 0b00 for the
PSIHB. This patch updates it, in case an hypervisor is in the mood of
checking it.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230703081215.55252-3-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 19d197f5d1e12717310110389267f16986763e9a
https://github.com/qemu/qemu/commit/19d197f5d1e12717310110389267f16986763e9a
Author: Joel Stanley <joel@jms.id.au>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: quad xscom callbacks are P9 specific
Rename the functions to include P9 in the name in preparation for adding
P10 versions.
Correct the unimp read message while we're changing the function.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-ID: <20230704054204.168547-2-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: fdc2b46abaa81415a8e6d8439bdd0c3d1b930373
https://github.com/qemu/qemu/commit/fdc2b46abaa81415a8e6d8439bdd0c3d1b930373
Author: Joel Stanley <joel@jms.id.au>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
Log Message:
-----------
ppc/pnv: Subclass quad xscom callbacks
Make the existing pnv_quad_xscom_read/write be P9 specific, in
preparation for a different P10 callback.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-ID: <20230704054204.168547-3-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a1d64b9efc8173e4e90aef5f48e89364c43118a5
https://github.com/qemu/qemu/commit/a1d64b9efc8173e4e90aef5f48e89364c43118a5
Author: Joel Stanley <joel@jms.id.au>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Add P10 quad xscom model
Add a PnvQuad class for the P10 powernv machine. No xscoms are
implemented yet, but this allows them to be added.
The size is reduced to avoid the quad region from overlapping with the
core region.
address-space: xscom-0
0000000000000000-00000003ffffffff (prio 0, i/o): xscom-0
0000000100000000-00000001000fffff (prio 0, i/o): xscom-quad.0
0000000100108000-0000000100907fff (prio 0, i/o): xscom-core.3
0000000100110000-000000010090ffff (prio 0, i/o): xscom-core.2
0000000100120000-000000010091ffff (prio 0, i/o): xscom-core.1
0000000100140000-000000010093ffff (prio 0, i/o): xscom-core.0
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-ID: <20230704054204.168547-4-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9a3942179d395d223531530d6ff71df25b00d064
https://github.com/qemu/qemu/commit/9a3942179d395d223531530d6ff71df25b00d064
Author: Joel Stanley <joel@jms.id.au>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: Add P10 core xscom model
Like the quad xscoms, add a core model for P10 to allow future
differentiation from P9.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-ID: <20230704054204.168547-5-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 53658074955efc7b4329999577464bd763ef4cbd
https://github.com/qemu/qemu/commit/53658074955efc7b4329999577464bd763ef4cbd
Author: Joel Stanley <joel@jms.id.au>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: Return zero for core thread state xscom
Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
this warning doesn't trigger, report the core thread state is 0.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-ID: <20230704054204.168547-6-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 053075097a053f7f9d8ce01f40ae1b1ad1845fea
https://github.com/qemu/qemu/commit/053075097a053f7f9d8ce01f40ae1b1ad1845fea
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
Log Message:
-----------
pnv/xive: Allow mmio operations of any size on the ESB CI pages
We currently only allow 64-bit operations on the ESB CI pages. There's
no real reason for that limitation, skiboot/linux didn't need
more. However the hardware supports any size, so this patch relaxes
that restriction. It impacts both the ESB pages for "normal"
interrupts as well as the ESB pages for escalation interrupts defined
for the ENDs.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230704144848.164287-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ebe0e9bbcbe432cd9fbcfbb4e2e9be86761ee606
https://github.com/qemu/qemu/commit/ebe0e9bbcbe432cd9fbcfbb4e2e9be86761ee606
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
ppc/pegasos2: Add support for -initrd command line option
This also changes type of sz local variable to ssize_t because it is
used to store return value of load_elf() and load_image_targphys() that
return ssize_t.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <20230704181920.27B58746335@zero.eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ff349cce8923d3c1713a6d58eb98ff692e6637f6
https://github.com/qemu/qemu/commit/ff349cce8923d3c1713a6d58eb98ff692e6637f6
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/intc/trace-events
M hw/intc/xive.c
Log Message:
-----------
pnv/xive: Print CPU target in all TIMA traces
Add the CPU target in the trace when reading/writing the TIMA
space. It was already done for other TIMA ops (notify, accept, ...),
only missing for those 2. Useful for debug and even more now that we
experiment with SMT.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230705110039.231148-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ed75a123579d56b5523f74868bb2c5877dc2c119
https://github.com/qemu/qemu/commit/ed75a123579d56b5523f74868bb2c5877dc2c119
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Always pass a presenter object when accessing the TIMA
The low-level functions to access the TIMA take a presenter object as
a first argument. When accessing the TIMA from the IC BAR,
i.e. indirect calls, we currently pass a NULL pointer for the
presenter argument. While it appears ok with the current usage, it's
dangerous. And it's pretty easy to figure out the presenter in that
context, so this patch fixes it.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230705081400.218408-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 3401ea3cfe06ab5ab059ae19b662270e1357545e
https://github.com/qemu/qemu/commit/3401ea3cfe06ab5ab059ae19b662270e1357545e
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/spapr_cpu_core.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/misc_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add LPAR-per-core vs per-thread mode flag
The Power ISA has the concept of sub-processors:
Hardware is allowed to sub-divide a multi-threaded processor into
"sub-processors" that appear to privileged programs as multi-threaded
processors with fewer threads.
POWER9 and POWER10 have two modes, either every thread is a
sub-processor or all threads appear as one multi-threaded processor. In
the user manuals these are known as "LPAR per thread" / "Thread LPAR",
and "LPAR per core" / "1 LPAR", respectively.
The practical difference is: in thread LPAR mode, non-hypervisor SPRs
are not shared between threads and msgsndp can not be used to message
siblings. In 1 LPAR mode, some SPRs are shared and msgsndp is usable.
Thrad LPAR allows multiple partitions to run concurrently on the same
core, and is a requirement for KVM to run on POWER9/10 (which does not
gang-schedule an LPAR on all threads of a core like POWER8 KVM).
Traditionally, SMT in PAPR environments including PowerVM and the
pseries QEMU machine with KVM acceleration behaves as in 1 LPAR mode.
In OPAL systems, Thread LPAR is used. When adding SMT to the powernv
machine, it is therefore preferable to emulate Thread LPAR.
To account for this difference between pseries and powernv, an LPAR mode
flag is added such that SPRs can be implemented as per-LPAR shared, and
that becomes either per-thread or per-core depending on the flag.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230705120631.27670-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9cdfd1b9f7eb5ecd1267bbd68330a11dcb8aa8f2
https://github.com/qemu/qemu/commit/9cdfd1b9f7eb5ecd1267bbd68330a11dcb8aa8f2
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/misc_helper.c
M target/ppc/spr_common.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: SMT support for the HID SPR
HID is a per-core shared register, skiboot sets this (e.g., setting
HILE) on one thread and that must affect all threads of the core.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230705120631.27670-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 934676c7b726fe9cccac02a7a4fa23c1e6a4c91e
https://github.com/qemu/qemu/commit/934676c7b726fe9cccac02a7a4fa23c1e6a4c91e
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M docs/system/ppc/powernv.rst
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: SMT support for powernv
Set the TIR default value with the SMT thread index, and place some
standard limits on SMT configurations. Now powernv is able to boot
skiboot and Linux with a SMT topology, including booting a KVM guest.
There are several SPRs and other features (e.g., broadcast msgsnd)
that are not implemented, but not used by OPAL or Linux and can be
added incrementally.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230705120631.27670-4-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2bef5b9452b2c6239c1e8512461ae900d5e8ebe6
https://github.com/qemu/qemu/commit/2bef5b9452b2c6239c1e8512461ae900d5e8ebe6
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
A tests/avocado/ppc_powernv.py
Log Message:
-----------
tests/avocado: Add powernv machine test script
This copies ppc_pseries.py to start a set of powernv tests, including
a Linux boot test for the newly added SMT mode.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230705120631.27670-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 339d13ce57a33d1536b0bae15ee633af11e6b116
https://github.com/qemu/qemu/commit/339d13ce57a33d1536b0bae15ee633af11e6b116
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440.h
M hw/ppc/ppc440_uc.c
M hw/ppc/sam460ex.c
Log Message:
-----------
ppc440: Change ppc460ex_pcie_init() parameter type
Change parameter of ppc460ex_pcie_init() from env to cpu to allow
further refactoring.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<1695d7cc1a9f1070ab498c078916e2389d6e9469.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 256f06668a7764a3bab581cd3b548964e3861189
https://github.com/qemu/qemu/commit/256f06668a7764a3bab581cd3b548964e3861189
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440: Add cpu link property to PCIe controller model
The PCIe controller model uses PPC DCRs but cannot be modeled with
TYPE_PPC4xx_DCR_DEVICE as it derives from TYPE_PCIE_HOST_BRIDGE. Add a
cpu link property to it similar to other DCR devices to allow
registering DCRs from the device model.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<a79796654deaa81a6a1c71efc874e4d88c4cafd4.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ca1ae3432f22c33401a0c8cbf4f7cd4cf13e8e6f
https://github.com/qemu/qemu/commit/ca1ae3432f22c33401a0c8cbf4f7cd4cf13e8e6f
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440: Add a macro to shorten PCIe controller DCR registration
It is shorter and more readable to wrap the complex call to
ppc_dcr_register() in a macro than to repeat it several times.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<4dec5ef8115791dc67253afdff9a703eb816a2a8.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 48bb07fbb1d9223448a4c11c6b711db0cf1fdc57
https://github.com/qemu/qemu/commit/48bb07fbb1d9223448a4c11c6b711db0cf1fdc57
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440: Rename parent field of PPC460EXPCIEState to match code style
QOM prefers to call the parent field parent_obj, change
PPC460EXPCIEState ro match that convention.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<6995f28215d2a489a661b7d91a1783048829d467.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b5d2ad84a14c1305efd9739d98a6adec0bf42e4d
https://github.com/qemu/qemu/commit/b5d2ad84a14c1305efd9739d98a6adec0bf42e4d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440: Rename local variable in dcr_read_pcie()
Rename local variable storing state struct in dcr_read_pcie() for
brevity and consistency with other functions.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<7b6f0033ada74075fc094b1397deb406e1a05741.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 088b61bc49fab767d73d79d49cb828d866346e6d
https://github.com/qemu/qemu/commit/088b61bc49fab767d73d79d49cb828d866346e6d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440: Stop using system io region for PCIe buses
Add separate memory regions for the mem and io spaces of the PCIe bus
to avoid different buses using the same system io region.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<b631c3a61729eee2166d899b8888164ebeb71574.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6ef62c5945316c265189e301b5fadf9285850221
https://github.com/qemu/qemu/commit/6ef62c5945316c265189e301b5fadf9285850221
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440: Add busnum property to PCIe controller model
Instead of guessing controller number from dcrn_base add a property so
the device does not need knowledge about where it is used.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<fdb84344025e00fadf74d0be95665fcb0ac1e039.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 340dc03c798d07fda7fd7f608dc224caa2909849
https://github.com/qemu/qemu/commit/340dc03c798d07fda7fd7f608dc224caa2909849
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440.h
M hw/ppc/ppc440_uc.c
M hw/ppc/sam460ex.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc440: Remove ppc460ex_pcie_init legacy init function
After previous changes we can now remove the legacy init function and
move the device creation to board code.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<29aafeea9f1c871c739600a7b093c5456e8a1dc8.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 41cd3e649be9f8f12aa2028623af916dd81d3403
https://github.com/qemu/qemu/commit/41cd3e649be9f8f12aa2028623af916dd81d3403
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/sam460ex.c
Log Message:
-----------
ppc/sam460ex: Remove address_space_mem local variable
Some places already use get_system_memory() directly so replace the
remaining uses and drop the local variable.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID:
<d134d64f13258d1f157b445fedb1e86cf3abb606.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 97784278880b58952400cafcfd1c12fc1c0b5124
https://github.com/qemu/qemu/commit/97784278880b58952400cafcfd1c12fc1c0b5124
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_pcix.c
Log Message:
-----------
ppc440_pcix: Don't use iomem for regs
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<3def68f200edd4540393d6b3b03baabe15d649f2.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: dd0f356dfe363d51b0cc0e1925db902b97338e18
https://github.com/qemu/qemu/commit/dd0f356dfe363d51b0cc0e1925db902b97338e18
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_pcix.c
M hw/ppc/sam460ex.c
Log Message:
-----------
ppc440_pcix: Stop using system io region for PCI bus
Reduce the iomem region to 64K and use it for the PCI io space and map
it directly from the board without an intermediate alias that is not
really needed.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<f4ad9af42197a92dd1d0b56c21316dbdad240ee4.1688641673.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e75a951b89382c77cc2bf63db5996cafa54adc3d
https://github.com/qemu/qemu/commit/e75a951b89382c77cc2bf63db5996cafa54adc3d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc4xx_pci.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx_pci: Rename QOM type name define
Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to
match each other and other similar types and to avoid confusion with
"ppc4xx-host-bridge" type defined in same file.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID:
<c59c28ef440633dbd1de0bda0a93b7862ef91104.1688641673.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2460bdff8ed704e1e922d327d15b535594893144
https://github.com/qemu/qemu/commit/2460bdff8ed704e1e922d327d15b535594893144
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_pcix.c
M hw/ppc/ppc4xx_pci.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx_pci: Add define for ppc4xx-host-bridge type name
Add a QOM type name define for ppc4xx-host-bridge in the common header
and replace direct use of the string name with the constant.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID:
<f6e2956b3a09ee481b970ef7873b374c846ba0a8.1688641673.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5efa7545205e8e9617afd8dc3cf0180943f975b7
https://github.com/qemu/qemu/commit/5efa7545205e8e9617afd8dc3cf0180943f975b7
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/ppc440_pcix.c
M hw/ppc/sam460ex.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc440_pcix: Rename QOM type define abd move it to common header
Rename TYPE_PPC440_PCIX_HOST_BRIDGE to better match its string value,
move it to common header and use it also in sam460ex to replace hard
coded type name.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID:
<1a1c3fe4b120f345d1005ad7ceca4500783691f7.1688641673.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b0afb574bad3c3a27acd2c3e7a17306a3648b0ac
https://github.com/qemu/qemu/commit/b0afb574bad3c3a27acd2c3e7a17306a3648b0ac
Author: Joel Stanley <joel@jms.id.au>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: Log all unimp warnings with similar message
Add the function name so there's an indication as to where the message
is coming from. Change all prints to use the offset instead of the
address.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230706024528.40065-1-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: aa2addf96f2629101ef0aa0c9226d38867c72d76
https://github.com/qemu/qemu/commit/aa2addf96f2629101ef0aa0c9226d38867c72d76
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Set P10 core xscom region size to match hardware
The P10 core xscom memory regions overlap because the size is wrong.
The P10 core+L2 xscom region size is allocated as 0x1000 (with some
unused ranges). "EC" is used as a closer match, as "EX" includes L3
which has a disjoint xscom range that would require a different
region if it were implemented.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230706053923.115003-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e1a821d47167a46e4386e763cd7e7901c856c4b2
https://github.com/qemu/qemu/commit/e1a821d47167a46e4386e763cd7e7901c856c4b2
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M tests/qtest/pnv-xscom-test.c
Log Message:
-----------
tests/qtest: Add xscom tests for powernv10 machine
Add basic chip and core xscom tests for powernv10 machine, equivalent
to tests for powernv8 and 9.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230706053923.115003-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 55a7fa34f8982f22497b2453787336acc7f79a7c
https://github.com/qemu/qemu/commit/55a7fa34f8982f22497b2453787336acc7f79a7c
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/internal.h
Log Message:
-----------
target/ppc: Machine check on invalid real address access on POWER9/10
ppc currently silently accepts invalid real address access. Catch
these and turn them into machine checks on POWER9/10 machines.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230703120301.45313-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 597645ccb570e3288f6937c7710be110b6c8f254
https://github.com/qemu/qemu/commit/597645ccb570e3288f6937c7710be110b6c8f254
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h'
"kvm_ppc.h" declares:
int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run);
'struct kvm_run' is declared in "sysemu/kvm.h", include it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230627115124.19632-2-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1b4b1bb5064dc08df6fd4ce9813b5f3370eda085
https://github.com/qemu/qemu/commit/1b4b1bb5064dc08df6fd4ce9813b5f3370eda085
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc: Reorder #ifdef'ry in kvm_ppc.h
Keep a single if/else/endif block checking CONFIG_KVM.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230627115124.19632-3-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 66453c0f0cbfcc64be3af1f738dd057a2be560da
https://github.com/qemu/qemu/commit/66453c0f0cbfcc64be3af1f738dd057a2be560da
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Move CPU QOM definitions to cpu-qom.h
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230627115124.19632-4-philmd@linaro.org>
[dhb: keep cpu_list define in target/ppc/cpu.h]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: be67dd4afea13b3a18fab142082a40a59df439ce
https://github.com/qemu/qemu/commit/be67dd4afea13b3a18fab142082a40a59df439ce
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h
TYPE_HOST_POWERPC_CPU is used in various places of cpu_init.c,
in order to restrict "kvm_ppc.h" to sysemu, move this QOM-related
definition to cpu-qom.h.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-ID: <20230627115124.19632-5-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: d0815cb808fe0cebe04aba5339e3f5cfe08cb4d7
https://github.com/qemu/qemu/commit/d0815cb808fe0cebe04aba5339e3f5cfe08cb4d7
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c
User emulation shouldn't need any of the KVM prototypes
declared in "kvm_ppc.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-ID: <20230627115124.19632-6-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9c1ce7723bbe18680f57ac318947fe7c7214d474
https://github.com/qemu/qemu/commit/9c1ce7723bbe18680f57ac318947fe7c7214d474
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h'
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-ID: <20230627115124.19632-7-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: bdb97596f663e9af9741353417c651f0d581de29
https://github.com/qemu/qemu/commit/bdb97596f663e9af9741353417c651f0d581de29
Author: Joel Stanley <joel@jms.id.au>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Add QME region for P10
The Quad Management Engine (QME) manages power related settings for its
quad. The xscom region is separate from the quad xscoms, therefore a new
region is added. The xscoms in a QME select a given core by selecting
the forth nibble.
Implement dummy reads for the stop state history (SSH) and special
wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
boots on p10.
Power9 does not have a QME.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-ID: <20230707071213.9924-1-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 276d72ca1b9017916cadc7c170d0d6b31633a9e5
https://github.com/qemu/qemu/commit/276d72ca1b9017916cadc7c170d0d6b31633a9e5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-07-07 (Fri, 07 Jul 2023)
Changed paths:
M docs/system/ppc/powernv.rst
M hw/intc/pnv_xive2.c
M hw/intc/trace-events
M hw/intc/xive.c
M hw/intc/xive2.c
M hw/net/sungem.c
M hw/net/trace-events
M hw/pci-host/mv64361.c
M hw/pci-host/mv643xx.h
M hw/ppc/pegasos2.c
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M hw/ppc/pnv_psi.c
M hw/ppc/ppc.c
M hw/ppc/ppc440.h
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc440_pcix.c
M hw/ppc/ppc440_uc.c
M hw/ppc/ppc4xx_pci.c
M hw/ppc/sam460ex.c
M hw/ppc/spapr_cpu_core.c
M include/hw/ppc/pnv_core.h
M include/hw/ppc/pnv_xscom.h
M include/hw/ppc/ppc4xx.h
M include/hw/ppc/xive.h
M target/ppc/arch_dump.c
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/internal.h
M target/ppc/kvm_ppc.h
M target/ppc/meson.build
M target/ppc/misc_helper.c
M target/ppc/spr_common.h
M target/ppc/timebase_helper.c
M target/ppc/translate.c
A tests/avocado/ppc_powernv.py
M tests/avocado/replay_kernel.py
M tests/qtest/pnv-xscom-test.c
Log Message:
-----------
Merge tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu into
staging
ppc patch queue for 2023-07-07:
In this last queue for 8.1 we have a lot of fixes and improvements all
around: SMT support for powerNV, XIVE fixes, PPC440 cleanups, exception
handling cleanups and kvm_pph.h cleanups just to name a few.
Thanks everyone in the qemu-ppc community for all the contributions for
the next QEMU 8.1 release.
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# gpg: Signature made Fri 07 Jul 2023 03:34:44 PM BST
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu: (59 commits)
ppc/pnv: Add QME region for P10
target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h'
target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c
target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h
target/ppc: Move CPU QOM definitions to cpu-qom.h
target/ppc: Reorder #ifdef'ry in kvm_ppc.h
target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h'
target/ppc: Machine check on invalid real address access on POWER9/10
tests/qtest: Add xscom tests for powernv10 machine
ppc/pnv: Set P10 core xscom region size to match hardware
ppc/pnv: Log all unimp warnings with similar message
ppc440_pcix: Rename QOM type define abd move it to common header
ppc4xx_pci: Add define for ppc4xx-host-bridge type name
ppc4xx_pci: Rename QOM type name define
ppc440_pcix: Stop using system io region for PCI bus
ppc440_pcix: Don't use iomem for regs
ppc/sam460ex: Remove address_space_mem local variable
ppc440: Remove ppc460ex_pcie_init legacy init function
ppc440: Add busnum property to PCIe controller model
ppc440: Stop using system io region for PCIe buses
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/3b08e40b7abf...276d72ca1b90