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[Qemu-commits] [qemu/qemu] 68a582: hw/arm/xilinx_zynq: Wire FIQ between
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 68a582: hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC |
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Date: |
Thu, 15 Feb 2024 09:37:12 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 68a5827b80117973714455c5aa16063ad1ffacb9
https://github.com/qemu/qemu/commit/68a5827b80117973714455c5aa16063ad1ffacb9
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/xilinx_zynq.c
Log Message:
-----------
hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
connect FIQ output of the GIC CPU interfaces to the CPU.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240130152548.17855-1-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 681dfc0d552963d4d598350d26097a692900b408
https://github.com/qemu/qemu/commit/681dfc0d552963d4d598350d26097a692900b408
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M linux-user/aarch64/target_prctl.h
Log Message:
-----------
linux-user/aarch64: Choose SYNC as the preferred MTE mode
The API does not generate an error for setting ASYNC | SYNC; that merely
constrains the selection vs the per-cpu default. For qemu linux-user,
choose SYNC as the default.
Cc: qemu-stable@nongnu.org
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 64c6e7444dff64b42d11b836b9aec9acfbe8ecc2
https://github.com/qemu/qemu/commit/64c6e7444dff64b42d11b836b9aec9acfbe8ecc2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Fix nregs computation in do_{ld,st}_zpa
The field is encoded as [0-3], which is convenient for
indexing our array of function pointers, but the true
value is [1-4]. Adjust before calling do_mem_zpa.
Add an assert, and move the comment re passing ZT to
the helper back next to the relevant code.
Cc: qemu-stable@nongnu.org
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b12a7671b6099a26ce5d5ab09701f151e21c112c
https://github.com/qemu/qemu/commit/b12a7671b6099a26ce5d5ab09701f151e21c112c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/internals.h
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Adjust and validate mtedesc sizem1
When we added SVE_MTEDESC_SHIFT, we effectively limited the
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 96fcc9982b4aad7aced7fbff046048bbccc6cb0c
https://github.com/qemu/qemu/commit/96fcc9982b4aad7aced7fbff046048bbccc6cb0c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate-sme.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Split out make_svemte_desc
Share code that creates mtedesc and embeds within simd_desc.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 623507ccfcfebb0f10229ae5de3f85a27fb615a7
https://github.com/qemu/qemu/commit/623507ccfcfebb0f10229ae5de3f85a27fb615a7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Handle mte in do_ldrq, do_ldro
These functions "use the standard load helpers", but
fail to clean_data_tbi or populate mtedesc.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 855f94eca80c85a99f459e36684ea2f98f6a3243
https://github.com/qemu/qemu/commit/855f94eca80c85a99f459e36684ea2f98f6a3243
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
Log Message:
-----------
target/arm: Fix SVE/SME gross MTE suppression checks
The TBI and TCMA bits are located within mtedesc, not desc.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f94d58f2608d2cae4a59f07c89e811ca8b6753e1
https://github.com/qemu/qemu/commit/f94d58f2608d2cae4a59f07c89e811ca8b6753e1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/pci-host/raven.c
Log Message:
-----------
hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
The raven_io_ops MemoryRegionOps is the only one in the source tree
which sets .valid.unaligned to indicate that it should support
unaligned accesses and which does not also set .impl.unaligned to
indicate that its read and write functions can do the unaligned
handling themselves. This is a problem, because at the moment the
core memory system does not implement the support for handling
unaligned accesses by doing a series of aligned accesses and
combining them (system/memory.c:access_with_adjusted_size() has a
TODO comment noting this).
Fortunately raven_io_read() and raven_io_write() will correctly deal
with the case of being passed an unaligned address, so we can fix the
missing unaligned access support by setting .impl.unaligned in the
MemoryRegionOps struct.
Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
Commit: dfae6d5eec0666648d7e4664ae6e40ebf5b80c7b
https://github.com/qemu/qemu/commit/dfae6d5eec0666648d7e4664ae6e40ebf5b80c7b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/block/tc58128.c
Log Message:
-----------
hw/block/tc58128: Don't emit deprecation warning under qtest
Suppress the deprecation warning when we're running under qtest,
to avoid "make check" including warning messages in its output.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
Commit: 83ae76cea3a2499f69f98bb90e98224b9a801926
https://github.com/qemu/qemu/commit/83ae76cea3a2499f69f98bb90e98224b9a801926
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
We deliberately don't include qtests_npcm7xx in qtests_aarch64,
because we already get the coverage of those tests via qtests_arm,
and we don't want to use extra CI minutes testing them twice.
In commit 327b680877b79c4b we added it to qtests_aarch64; revert
that change.
Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
Commit: 6c1c2e912fcf915bfaf04ef42cbfe593c2df352f
https://github.com/qemu/qemu/commit/6c1c2e912fcf915bfaf04ef42cbfe593c2df352f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/qtest/bios-tables-test: Allow changes to virt GTDT
Allow changes to the virt GTDT -- we are going to add the IRQ
entry for a new timer to it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
Commit: 1ec896fe7ca938276aea8cadc677263f7a3264bb
https://github.com/qemu/qemu/commit/1ec896fe7ca938276aea8cadc677263f7a3264bb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
non-secure EL2 virtual timer. We implemented the timer itself in the
CPU model, but never wired up its IRQ line to the GIC.
Wire up the IRQ line (this is always safe whether the CPU has the
interrupt or not, since it always creates the outbound IRQ line).
Report it to the guest via dtb and ACPI if the CPU has the feature.
The DTB binding is documented in the kernel's
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
and the ACPI table entries are documented in the ACPI specification
version 6.3 or later.
Because the IRQ line ACPI binding is new in 6.3, we need to bump the
FADT table rev to show that we might be using 6.3 features.
Note that exposing this IRQ in the DTB will trigger a bug in EDK2
versions prior to edk2-stable202311, for users who use the virt board
with 'virtualization=on' to enable EL2 emulation and are booting an
EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is
that EDK2 will assert on bootup:
ASSERT [ArmTimerDxe]
/home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72):
PropSize == 36 || PropSize == 48
If you see that assertion you should do one of:
* update your EDK2 binaries to edk2-stable202311 or newer
* use the 'virt-8.2' versioned machine type
* not use 'virtualization=on'
(The versions shipped with QEMU itself have the fix.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
Commit: ea2fde5bccc514d9072eec740ecb4d5d870b4231
https://github.com/qemu/qemu/commit/ea2fde5bccc514d9072eec740ecb4d5d870b4231
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M tests/data/acpi/virt/FACP
M tests/data/acpi/virt/GTDT
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/qtest/bios-tables-tests: Update virt golden reference
Update the virt golden reference files to say that the FACP is ACPI
v6.3, and the GTDT table is a revision 3 table with space for the
virtual EL2 timer.
Diffs from iasl:
@@ -1,32 +1,32 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
[004h 0004 4] Table Length : 00000114
[008h 0008 1] Revision : 06
-[009h 0009 1] Checksum : 15
+[009h 0009 1] Checksum : 12
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] FACS Address : 00000000
[028h 0040 4] DSDT Address : 00000000
[02Ch 0044 1] Model : 00
[02Dh 0045 1] PM Profile : 00 [Unspecified]
[02Eh 0046 2] SCI Interrupt : 0000
[030h 0048 4] SMI Command Port : 00000000
[034h 0052 1] ACPI Enable Value : 00
[035h 0053 1] ACPI Disable Value : 00
[036h 0054 1] S4BIOS Command : 00
[037h 0055 1] P-State Control : 00
@@ -86,33 +86,33 @@
Use APIC Physical Destination Mode (V4) : 0
Hardware Reduced (V5) : 1
Low Power S0 Idle (V5) : 0
[074h 0116 12] Reset Register : [Generic Address Structure]
[074h 0116 1] Space ID : 00 [SystemMemory]
[075h 0117 1] Bit Width : 00
[076h 0118 1] Bit Offset : 00
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
[078h 0120 8] Address : 0000000000000000
[080h 0128 1] Value to cause reset : 00
[081h 0129 2] ARM Flags (decoded below) : 0003
PSCI Compliant : 1
Must use HVC for PSCI : 1
-[083h 0131 1] FADT Minor Revision : 00
+[083h 0131 1] FADT Minor Revision : 03
[084h 0132 8] FACS Address : 0000000000000000
[08Ch 0140 8] DSDT Address : 0000000000000000
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
[094h 0148 1] Space ID : 00 [SystemMemory]
[095h 0149 1] Bit Width : 00
[096h 0150 1] Bit Offset : 00
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
[098h 0152 8] Address : 0000000000000000
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
[0A0h 0160 1] Space ID : 00 [SystemMemory]
[0A1h 0161 1] Bit Width : 00
[0A2h 0162 1] Bit Offset : 00
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
[0A4h 0164 8] Address : 0000000000000000
@@ -164,34 +164,34 @@
[0F5h 0245 1] Bit Width : 00
[0F6h 0246 1] Bit Offset : 00
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
[0F8h 0248 8] Address : 0000000000000000
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
[100h 0256 1] Space ID : 00 [SystemMemory]
[101h 0257 1] Bit Width : 00
[102h 0258 1] Bit Offset : 00
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
[104h 0260 8] Address : 0000000000000000
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
Raw Table Data: Length 276 (0x114)
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
0110: 00 00 00 00 // ....
@@ -1,32 +1,32 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
*
* ACPI Data Table [GTDT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "GTDT" [Generic Timer
Description Table]
-[004h 0004 4] Table Length : 00000060
-[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : 9C
+[004h 0004 4] Table Length : 00000068
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 93
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
[02Ch 0044 4] Reserved : 00000000
[030h 0048 4] Secure EL1 Interrupt : 0000001D
[034h 0052 4] EL1 Flags (decoded below) : 00000000
Trigger Mode : 0
Polarity : 0
Always On : 0
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
@@ -37,25 +37,28 @@
[040h 0064 4] Virtual Timer Interrupt : 0000001B
[044h 0068 4] VT Flags (decoded below) : 00000000
Trigger Mode : 0
Polarity : 0
Always On : 0
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
Trigger Mode : 0
Polarity : 0
Always On : 0
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
[058h 0088 4] Platform Timer Count : 00000000
[05Ch 0092 4] Platform Timer Offset : 00000000
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
-Raw Table Data: Length 96 (0x60)
+Raw Table Data: Length 104 (0x68)
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 // ........
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
Commit: 243f865af95db55f30c8547b407b3420909590a7
https://github.com/qemu/qemu/commit/243f865af95db55f30c8547b407b3420909590a7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/npcm7xx.c
Log Message:
-----------
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
The patchset adding the GMAC ethernet to this SoC crossed in the
mail with the patchset cleaning up the NIC handling. When we
create the GMAC modules we must call qemu_configure_nic_device()
so that the user has the opportunity to use the -nic commandline
option to create a network backend and connect it to the GMACs.
Add the missing call.
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
Commit: bf25d7815b0c0d58c43c3301d8debf1c75727547
https://github.com/qemu/qemu/commit/bf25d7815b0c0d58c43c3301d8debf1c75727547
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M tests/qtest/npcm7xx_emc-test.c
Log Message:
-----------
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
Currently QEMU will warn if there is a NIC on the board that
is not connected to a backend. By default the '-nic user' will
get used for all NICs, but if you manually connect a specific
NIC to a specific backend, then the other NICs on the board
have no backend and will be warned about:
qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
qemu-system-arm: warning: nic npcm-gmac.1 has no peer
So suppress those warnings by manually connecting every NIC
on the board to some backend.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
Commit: ac1d88e9e7ca0bed83e91e07ce6d0597f10cc77d
https://github.com/qemu/qemu/commit/ac1d88e9e7ca0bed83e91e07ce6d0597f10cc77d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking
ARM_FEATURE_PMU
It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
CPU, and in fact if you try to do it we will assert:
#6 0x00007ffff4b95e96 in __GI___assert_fail
(assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)",
file=0x5555565a6e5c "../../target/arm/helper.c", line=12600,
function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3")
at ./assert/assert.c:101
#7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at
../../target/arm/helper.c:12600
#8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at
../../target/arm/cpu.h:2595
#9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at
../../target/arm/internals.h:1512
We might call pmu_counter_enabled() on an M-profile CPU (for example
from the migration pre/post hooks in machine.c); this should always
return false because these CPUs don't set ARM_FEATURE_PMU.
Avoid the assertion by not calling arm_mdcr_el2_eff() before we
have done the early return for "PMU not present".
This fixes an assertion failure if you try to do a loadvm or
savevm for an M-profile board.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
Commit: bfe30b02e7018ff0fa9fd8a7342ce5c4cb5ca40c
https://github.com/qemu/qemu/commit/bfe30b02e7018ff0fa9fd8a7342ce5c4cb5ca40c
Author: Nabih Estefan <nabihestefan@google.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M tests/qtest/meson.build
M tests/qtest/npcm_gmac-test.c
Log Message:
-----------
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
of 8xx. Also fix comments referencing this and values expecting 8xx.
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: commit message tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 15f6c16e6e4b418a1dabad6704917bdb6ee883f4
https://github.com/qemu/qemu/commit/15f6c16e6e4b418a1dabad6704917bdb6ee883f4
Author: Luc Michel <luc.michel@amd.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmuv3: add support for stage 1 access fault
An access fault is raised when the Access Flag is not set in the
looked-up PTE and the AFFD field is not set in the corresponding context
descriptor. This was already implemented for stage 2. Implement it for
stage 1 as well.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Mostafa Saleh <smostafa@google.com>
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
[PMM: tweaked comment text]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bebd89e1661a0ebfcc4a6f6a8c2786f444c4e60f
https://github.com/qemu/qemu/commit/bebd89e1661a0ebfcc4a6f6a8c2786f444c4e60f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
hw/arm/stellaris: Convert ADC controller to Resettable interface
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240213155214.13619-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cee78fa5134d7193b3185b9ddb86cefd5967c5f8
https://github.com/qemu/qemu/commit/cee78fa5134d7193b3185b9ddb86cefd5967c5f8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
hw/arm/stellaris: Convert I2C controller to Resettable interface
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240213155214.13619-3-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7e4a8d9dbeafc89f6a1e2ea6f7a9b0b8979f33d7
https://github.com/qemu/qemu/commit/7e4a8d9dbeafc89f6a1e2ea6f7a9b0b8979f33d7
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
hw/arm/stellaris: Add missing QOM 'machine' parent
QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().
This commit plug the devices which aren't part of the SoC;
they will be plugged into a SoC container in the next one.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240213155214.13619-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 243b8602a6de74fbb56ede18e02ffb8b9de3b386
https://github.com/qemu/qemu/commit/243b8602a6de74fbb56ede18e02ffb8b9de3b386
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
hw/arm/stellaris: Add missing QOM 'SoC' parent
QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().
Since we don't model the SoC, just use a QOM container.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240213155214.13619-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b2f24983db11dd1345db95f54a6d1dce184224a3
https://github.com/qemu/qemu/commit/b2f24983db11dd1345db95f54a6d1dce184224a3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
We support two different encodings for the AArch32 IMPDEF
CBAR register -- older cores like the Cortex A9, A7, A15
have this at 4, c15, c0, 0; newer cores like the
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
When we implemented this we picked which encoding to
use based on whether the CPU set ARM_FEATURE_AARCH64.
However this isn't right for three cases:
* the qemu-system-arm 'max' CPU, which is supposed to be
a variant on a Cortex-A57; it ought to use the same
encoding the A57 does and which the AArch64 'max'
exposes to AArch32 guest code
* the Cortex-R52, which is AArch32-only but has the CBAR
at the newer encoding (and where we incorrectly are
not yet setting ARM_FEATURE_CBAR_RO anyway)
* any possible future support for other v8 AArch32
only CPUs, or for supporting "boot the CPU into
AArch32 mode" on our existing cores like the A57 etc
Make the decision of the encoding be based on whether
the CPU implements the ARM_FEATURE_V8 flag instead.
This changes the behaviour only for the qemu-system-arm
'-cpu max'. We don't expect anybody to be relying on the
old behaviour because:
* it's not what the real hardware Cortex-A57 does
(and that's what our ID register claims we are)
* we don't implement the memory-mapped GICv3 support
which is the only thing that exists at the peripheral
base address pointed to by the register
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
Commit: fe31d6c72d0046eb633db51dc1d8fb9b231d270f
https://github.com/qemu/qemu/commit/fe31d6c72d0046eb633db51dc1d8fb9b231d270f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/tcg/cpu32.c
Log Message:
-----------
target/arm: The Cortex-R52 has a read-only CBAR
The Cortex-R52 implements the Configuration Base Address Register
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
type, so that our implementation provides the register and the
associated qdev property.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
Commit: 282a48eca4c84c3f146165aab3a64e82b4b60670
https://github.com/qemu/qemu/commit/282a48eca4c84c3f146165aab3a64e82b4b60670
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/tcg/cpu32.c
Log Message:
-----------
target/arm: Add Cortex-R52 IMPDEF sysregs
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
also by enabling the AUXCR feature which defines the ACTLR
and HACTLR registers. As is our usual practice, we make these
simple reads-as-zero stubs for now.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
Commit: f2b4a98930c122648e9dc494e49cea5dffbcc2be
https://github.com/qemu/qemu/commit/f2b4a98930c122648e9dc494e49cea5dffbcc2be
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/arm/tcg/op_helper.c
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Allow access to SPSR_hyp from hyp mode
Architecturally, the AArch32 MSR/MRS to/from banked register
instructions are UNPREDICTABLE for attempts to access a banked
register that the guest could access in a more direct way (e.g.
using this insn to access r8_fiq when already in FIQ mode). QEMU has
chosen to UNDEF on all of these.
However, for the case of accessing SPSR_hyp from hyp mode, it turns
out that real hardware permits this, with the same effect as if the
guest had directly written to SPSR. Further, there is some
guest code out there that assumes it can do this, because it
happens to work on hardware: an example Cortex-R52 startup code
fragment uses this, and it got copied into various other places,
including Zephyr. Zephyr was fixed to not use this:
https://github.com/zephyrproject-rtos/zephyr/issues/47330
but other examples are still out there, like the selftest
binary for the MPS3-AN536.
For convenience of being able to run guest code, permit
this UNPREDICTABLE access instead of UNDEFing it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
Commit: a72e625078d4766367510887552f8c2f49bd7039
https://github.com/qemu/qemu/commit/a72e625078d4766367510887552f8c2f49bd7039
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/misc/mps2-scc.c
Log Message:
-----------
hw/misc/mps2-scc: Fix condition for CFG3 register
We currently guard the CFG3 register read with
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
which is clearly wrong as it is never true.
This register is present on all board types except AN524
and AN527; correct the condition.
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
Commit: 5f3bbbdbd0d2c87855936c20b78f1e538802bcd9
https://github.com/qemu/qemu/commit/5f3bbbdbd0d2c87855936c20b78f1e538802bcd9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/misc/mps2-scc.c
Log Message:
-----------
hw/misc/mps2-scc: Factor out which-board conditionals
The MPS SCC device has a lot of different flavours for the various
different MPS FPGA images, which look mostly similar but have
differences in how particular registers are handled. Currently we
deal with this with a lot of open-coded checks on scc_partno(), but
as we add more board types this is getting a bit hard to read.
Factor out the conditions into some functions which we can
give more descriptive names to.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
Commit: 2a5ee4e18de79e18b895804a7af34b7841b8563b
https://github.com/qemu/qemu/commit/2a5ee4e18de79e18b895804a7af34b7841b8563b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/misc/mps2-scc.c
M include/hw/misc/mps2-scc.h
Log Message:
-----------
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
The MPS2 SCC device is broadly the same for all FPGA images, but has
minor differences in the behaviour of the CFG registers depending on
the image. In many cases we don't really care about the functionality
controlled by these registers and a reads-as-written or similar
behaviour is sufficient for the moment.
For the AN536 the required behaviour is:
* A_CFG0 has CPU reset and halt bits
- implement as reads-as-written for the moment
* A_CFG1 has flash or ATCM address 0 remap handling
- QEMU doesn't model this; implement as reads-as-written
* A_CFG2 has QSPI select (like AN524)
- implemented (no behaviour, as with AN524)
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
- QEMU doesn't care about these, so use the existing
RAZ behaviour for convenience
* A_CFG4 is board rev (like all other images)
- no change needed
* A_CFG5 is ACLK frq in hz (like AN524)
- implemented as reads-as-written, as for other boards
* A_CFG6 is core 0 vector table base address
- implemented as reads-as-written for the moment
* A_CFG7 is core 1 vector table base address
- implemented as reads-as-written for the moment
Make the changes necessary for this; leave TODO comments where
appropriate to indicate where we might want to come back and
implement things like CPU reset.
The other aspects of the device specific to this FPGA image (like the
values of the board ID and similar registers) will be set via the
device's qdev properties.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
Commit: 273a70ae823768081084d51a780e18f9ad80d68e
https://github.com/qemu/qemu/commit/273a70ae823768081084d51a780e18f9ad80d68e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M MAINTAINERS
M configs/devices/arm-softmmu/default.mak
M hw/arm/Kconfig
M hw/arm/meson.build
A hw/arm/mps3r.c
Log Message:
-----------
hw/arm/mps3r: Initial skeleton for mps3-an536 board
The AN536 is another FPGA image for the MPS3 development board. Unlike
the existing FPGA images we already model, this board uses a Cortex-R
family CPU, and it does not use any equivalent to the M-profile
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
It's therefore more convenient for us to model it as a completely
separate C file.
This commit adds the basic skeleton of the board model, and the
code to create all the RAM and ROM. We assume that we're probably
going to want to add more images in future, so use the same
base class/subclass setup that mps2-tz.c uses, even though at
the moment there's only a single subclass.
Following commits will add the CPUs and the peripherals.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
Commit: 9220b09d3b1294967be67b1baeeb928187245594
https://github.com/qemu/qemu/commit/9220b09d3b1294967be67b1baeeb928187245594
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/mps3r.c
Log Message:
-----------
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
Create the CPUs, the GIC, and the per-CPU RAM block for
the mps3-an536 board.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
Commit: a71e26461464fc50ef84279dc7fceb40960182c1
https://github.com/qemu/qemu/commit/a71e26461464fc50ef84279dc7fceb40960182c1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/mps3r.c
Log Message:
-----------
hw/arm/mps3r: Add UARTs
This board has a lot of UARTs: there is one UART per CPU in the
per-CPU peripheral part of the address map, whose interrupts are
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
normal part of the peripheral space, whose interrupts are shared
peripheral interrupts.
Connect and wire them all up; this involves some OR gates where
multiple overflow interrupts are wired into one GIC input.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
Commit: 0482e76289f8a5fc70f87e5be799c72853fac11a
https://github.com/qemu/qemu/commit/0482e76289f8a5fc70f87e5be799c72853fac11a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/mps3r.c
Log Message:
-----------
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
board. These are all simple devices that just need to be created and
wired up.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
Commit: 82e2b7e354686fe3a35ffc57f1de8242dbb7ff13
https://github.com/qemu/qemu/commit/82e2b7e354686fe3a35ffc57f1de8242dbb7ff13
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/mps3r.c
Log Message:
-----------
hw/arm/mps3r: Add remaining devices
Add the remaining devices (or unimplemented-device stubs) for
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
QSPI write-config block, and ethernet.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
Commit: f780e63fe731b058fe52d43653600d8729a1b5f2
https://github.com/qemu/qemu/commit/f780e63fe731b058fe52d43653600d8729a1b5f2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M docs/system/arm/mps2.rst
Log Message:
-----------
docs: Add documentation for the mps3-an536 board
Add documentation for the mps3-an536 board type.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
Commit: cc29c12ec629ba68a4a6cb7d165c94cc8502815a
https://github.com/qemu/qemu/commit/cc29c12ec629ba68a4a6cb7d165c94cc8502815a
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M tests/qemu-iotests/144
M tests/qemu-iotests/144.out
Log Message:
-----------
iotests: Make 144 deterministic again
Since commit effd60c8 changed how QMP commands are processed, the order
of the block-commit return value and job events in iotests 144 wasn't
fixed and more and caused the test to fail intermittently.
Change the test to cache events first and then print them in a
predefined order.
Waiting three times for JOB_STATUS_CHANGE is a bit uglier than just
waiting for the JOB_STATUS_CHANGE that has "status": "ready", but the
tooling we have doesn't seem to allow the latter easily.
Fixes: effd60c878176bcaf97fa7ce2b12d04bb8ead6f7
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2126
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 20240209173103.239994-1-kwolf@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3ff11e4dcabe2b5b4c26e49d741018ec326f127f
https://github.com/qemu/qemu/commit/3ff11e4dcabe2b5b4c26e49d741018ec326f127f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M MAINTAINERS
M configs/devices/arm-softmmu/default.mak
M docs/system/arm/mps2.rst
M hw/arm/Kconfig
M hw/arm/meson.build
A hw/arm/mps3r.c
M hw/arm/npcm7xx.c
M hw/arm/smmu-common.c
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M hw/arm/stellaris.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/arm/xilinx_zynq.c
M hw/block/tc58128.c
M hw/misc/mps2-scc.c
M hw/pci-host/raven.c
M include/hw/arm/smmu-common.h
M include/hw/arm/virt.h
M include/hw/misc/mps2-scc.h
M linux-user/aarch64/target_prctl.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/tcg/cpu32.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate-sme.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/translate.c
M tests/data/acpi/virt/FACP
M tests/data/acpi/virt/GTDT
M tests/qtest/meson.build
M tests/qtest/npcm7xx_emc-test.c
M tests/qtest/npcm_gmac-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240215' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
* linux-user/aarch64: Choose SYNC as the preferred MTE mode
* Fix some errors in SVE/SME handling of MTE tags
* hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
* hw/block/tc58128: Don't emit deprecation warning under qtest
* tests/qtest: Fix handling of npcm7xx and GMAC tests
* hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
* tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
* Don't assert on vmload/vmsave of M-profile CPUs
* hw/arm/smmuv3: add support for stage 1 access fault
* hw/arm/stellaris: QOM cleanups
* Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
* Improve Cortex_R52 IMPDEF sysreg modelling
* Allow access to SPSR_hyp from hyp mode
* New board model mps3-an536 (Cortex-R52)
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# gpg: Signature made Thu 15 Feb 2024 17:33:08 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240215' of
https://git.linaro.org/people/pmaydell/qemu-arm: (35 commits)
docs: Add documentation for the mps3-an536 board
hw/arm/mps3r: Add remaining devices
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
hw/arm/mps3r: Add UARTs
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
hw/arm/mps3r: Initial skeleton for mps3-an536 board
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
hw/misc/mps2-scc: Factor out which-board conditionals
hw/misc/mps2-scc: Fix condition for CFG3 register
target/arm: Allow access to SPSR_hyp from hyp mode
target/arm: Add Cortex-R52 IMPDEF sysregs
target/arm: The Cortex-R52 has a read-only CBAR
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
hw/arm/stellaris: Add missing QOM 'SoC' parent
hw/arm/stellaris: Add missing QOM 'machine' parent
hw/arm/stellaris: Convert I2C controller to Resettable interface
hw/arm/stellaris: Convert ADC controller to Resettable interface
hw/arm/smmuv3: add support for stage 1 access fault
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking
ARM_FEATURE_PMU
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/5767815218ef...3ff11e4dcabe
- [Qemu-commits] [qemu/qemu] 68a582: hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC,
Peter Maydell <=