[Qemu-commits] [qemu/qemu] 181d92: docs/system: Update description for input grab key

[Alex Bennée]

  Branch: refs/heads/staging-7.2
  Home:   https://github.com/qemu/qemu
  Commit: 181d92d03419a34f53eedf15517e9ec3200a98b2
      
https://github.com/qemu/qemu/commit/181d92d03419a34f53eedf15517e9ec3200a98b2
  Author: Tianlan Zhou <bobby825@126.com>
  Date:   2024-02-22 (Thu, 22 Feb 2024)

  Changed paths:
    M docs/system/keys.rst.inc

  Log Message:
  -----------
  docs/system: Update description for input grab key

Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.

Fixes: f8d2c9369b ("sdl: use ctrl-alt-g as grab hotkey")
Signed-off-by: Tianlan Zhou <bobby825@126.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
(cherry picked from commit 4a20ac400ff0753f159071764826b20e5320cde9)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: 7f368bccd6d94b1f841c13b987efac39b7d1d37c
      
https://github.com/qemu/qemu/commit/7f368bccd6d94b1f841c13b987efac39b7d1d37c
  Author: Tianlan Zhou <bobby825@126.com>
  Date:   2024-02-22 (Thu, 22 Feb 2024)

  Changed paths:
    M softmmu/vl.c

  Log Message:
  -----------
  system/vl: Update description for input grab key

Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.

Fixes: f8d2c9369b ("sdl: use ctrl-alt-g as grab hotkey")
Signed-off-by: Tianlan Zhou <bobby825@126.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
(cherry picked from commit 185311130f54ead75c407cdf83004d575829b5d2)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: 1bdf3f4ba0c961f35eb50bf4fa7a3ad4da716c68
      
https://github.com/qemu/qemu/commit/1bdf3f4ba0c961f35eb50bf4fa7a3ad4da716c68
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-02-22 (Thu, 22 Feb 2024)

  Changed paths:
    M .gitlab-ci.d/windows.yml

  Log Message:
  -----------
  .gitlab-ci.d/windows.yml: Drop msys2-32bit job

MSYS2 is dropping support for 32-bit Windows.  This shows up for us
as various packages we were using in our CI job no longer being
available to install, which causes the job to fail.  In commit
8e31b744fdf we dropped the dependency on libusb and spice, but the
dtc package has also now been removed.

For us as QEMU upstream, "32 bit x86 hosts for system emulation" have
already been deprecated as of QEMU 8.0, so we are ready to drop them
anyway.

Drop the msys2-32bit CI job, as the first step in doing this.

This is cc'd to stable, because this job will also be broken for CI
on the stable branches.  We can't drop 32-bit support entirely there,
but we will still be covering at least compilation for 32-bit Windows
via the cross-win32-system job.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20240220165602.135695-1-peter.maydell@linaro.org
(cherry picked from commit 5cd3ae4903e33982e7a9bbd04674af517e796d6e)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
(Mjt: in 7.2 the piece being removed is different but the job has to go anyway)


  Commit: a15b7df35bf279b1328ee6b7939c8384aa1d364c
      
https://github.com/qemu/qemu/commit/a15b7df35bf279b1328ee6b7939c8384aa1d364c
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2024-02-24 (Sat, 24 Feb 2024)

  Changed paths:
    M target/ppc/translate/vsx-impl.c.inc

  Log Message:
  -----------
  target/ppc: Fix lxv/stxv MSR facility check

The move to decodetree flipped the inequality test for the VEC / VSX
MSR facility check.

This caused application crashes under Linux, where these facility
unavailable interrupts are used for lazy-switching of VEC/VSX register
sets. Getting the incorrect interrupt would result in wrong registers
being loaded, potentially overwriting live values and/or exposing
stale ones.

Cc: qemu-stable@nongnu.org
Reported-by: Joel Stanley <joel@jms.id.au>
Fixes: 70426b5bb738 ("target/ppc: moved stxvx and lxvx from legacy to 
decodtree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1769
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Tested-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

(cherry picked from commit 2cc0e449d17310877fb28a942d4627ad22bb68ea)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: d3c3bc7a9c9700a9dfcaa3266ea830d73744fa9d
      
https://github.com/qemu/qemu/commit/d3c3bc7a9c9700a9dfcaa3266ea830d73744fa9d
  Author: Klaus Jensen <k.jensen@samsung.com>
  Date:   2024-02-27 (Tue, 27 Feb 2024)

  Changed paths:
    M hw/nvme/ctrl.c

  Log Message:
  -----------
  hw/nvme: fix invalid endian conversion

numcntl is one byte and so is max_vfs. Using cpu_to_le16 on big endian
hosts results in numcntl being set to 0.

Fix by dropping the endian conversion.

Fixes: 99f48ae7ae ("hw/nvme: Add support for Secondary Controller List")
Reported-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Minwoo Im <minwoo.im@samsung.com>
Message-ID: <20240222-fix-sriov-numcntl-v1-1-d60bea5e72d0@samsung.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
(cherry picked from commit d2b5bb860e6c17442ad95cc275feb07c1665be5c)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: 77f7beb8cfe6266a5823737028809f749be608f3
      
https://github.com/qemu/qemu/commit/77f7beb8cfe6266a5823737028809f749be608f3
  Author: Jessica Clarke <jrtc27@jrtc27.com>
  Date:   2024-02-27 (Tue, 27 Feb 2024)

  Changed paths:
    M hw/rtc/pl031.c

  Log Message:
  -----------
  pl031: Update last RTCLR value on write in case it's read back

The PL031 allows you to read RTCLR, which is meant to give you the last
value written. PL031State has an lr field which is used when reading
from RTCLR, and is present in the VM migration state, but we never
actually update it, so it always reads as its initial 0 value.

Cc: qemu-stable@nongnu.org
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20240222000341.1562443-1-jrtc27@jrtc27.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 4d28d57c9f2eb1cdf70b29cea6e50282e010075b)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: 6156ca0da12c545cf6be0a964ebdac4b8eb50f2b
      
https://github.com/qemu/qemu/commit/6156ca0da12c545cf6be0a964ebdac4b8eb50f2b
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M target/i386/tcg/sysemu/excp_helper.c

  Log Message:
  -----------
  target/i386: mask high bits of CR3 in 32-bit mode

CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level
paging or PAE paging).  Do this in mmu_translate() to remove
the last where get_physical_address() meaningfully drops the high
bits of the address.

Cc: qemu-stable@nongnu.org
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 
2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 68fb78d7d5723066ec2cacee7d25d67a4143b42f)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: 5eba614159d17a6916f33ff9a088e8fb230181c2
      
https://github.com/qemu/qemu/commit/5eba614159d17a6916f33ff9a088e8fb230181c2
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M target/i386/tcg/sysemu/misc_helper.c
    M target/i386/tcg/sysemu/svm_helper.c

  Log Message:
  -----------
  target/i386: check validity of VMCB addresses

MSR_VM_HSAVE_PA bits 0-11 are reserved, as are the bits above the
maximum physical address width of the processor.  Setting them to
1 causes a #GP (see "15.30.4 VM_HSAVE_PA MSR" in the AMD manual).

The same is true of VMCB addresses passed to VMRUN/VMLOAD/VMSAVE,
even though the manual is not clear on that.

Cc: qemu-stable@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 
2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit d09c79010ffd880dc69e7a21e3cfdef90b928fb8)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: 1c15f97b4f1957e75f1ef6638ca6772d21f86ec4
      
https://github.com/qemu/qemu/commit/1c15f97b4f1957e75f1ef6638ca6772d21f86ec4
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M target/i386/cpu.h
    M target/i386/tcg/sysemu/excp_helper.c

  Log Message:
  -----------
  target/i386: Fix physical address truncation

The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using PAE
to access memory above 4G will experience undefined behaviour.

The truncation code was originally introduced in commit 33dfdb5 ("x86:
only allow real mode to access 32bit without LMA"), where it applied
only to translations performed while paging is disabled (and so cannot
affect guests using PAE).

Commit 9828198 ("target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX")
rearranged the code such that the truncation also applied to the use
of MMU_PHYS_IDX and MMU_NESTED_IDX.  Commit 4a1e9d4 ("target/i386: Use
atomic operations for pte updates") brought this truncation into scope
for page table entry accesses, and is the first commit for which a
Windows 10 32-bit guest will reliably fail to boot if memory above 4G
is present.

The truncation code however is not completely redundant.  Even though the
maximum address size for any executed instruction is 32 bits, helpers for
operations such as BOUND, FSAVE or XSAVE may ask get_physical_address()
to translate an address outside of the 32-bit range, if invoked with an
argument that is close to the 4G boundary.  Likewise for processor
accesses, for example TSS or IDT accesses, when EFER.LMA==0.

So, move the address truncation in get_physical_address() so that it
applies to 32-bit MMU indexes, but not to MMU_PHYS_IDX and MMU_NESTED_IDX.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2040
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 
2022-10-18)
Cc: qemu-stable@nongnu.org
Co-developed-by: Michael Brown <mcb30@ipxe.org>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit b1661801c184119a10ad6cbc3b80330fc22e7b2c)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
(Mjt: drop unrelated change in target/i386/cpu.c)


  Commit: 91ad0d26e1e8e780a2b5c2d464c1f05ef2a7f7f5
      
https://github.com/qemu/qemu/commit/91ad0d26e1e8e780a2b5c2d464c1f05ef2a7f7f5
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M target/i386/tcg/sysemu/excp_helper.c

  Log Message:
  -----------
  target/i386: remove unnecessary/wrong application of the A20 mask

If ptw_translate() does a MMU_PHYS_IDX access, the A20 mask is already
applied in get_physical_address(), which is called via probe_access_full()
and x86_cpu_tlb_fill().

If ptw_translate() on the other hand does a MMU_NESTED_IDX access,
the A20 mask must not be applied to the address that is looked up in
the nested page tables; it must be applied only to the addresses that
hold the NPT entries (which is achieved via MMU_PHYS_IDX, per the
previous paragraph).

Therefore, we can remove A20 masking from the computation of the page
table entry's address, and let get_physical_address() or mmu_translate()
apply it when they know they are returning a host-physical address.

Cc: qemu-stable@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 
2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit a28fe7dc1939333c81b895cdced81c69eb7c5ad0)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: 1165d9601def8120c4b5c9f10b7fb28f28e77135
      
https://github.com/qemu/qemu/commit/1165d9601def8120c4b5c9f10b7fb28f28e77135
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M target/i386/tcg/sysemu/excp_helper.c

  Log Message:
  -----------
  target/i386: leave the A20 bit set in the final NPT walk

The A20 mask is only applied to the final memory access.  Nested
page tables are always walked with the raw guest-physical address.

Unlike the previous patch, in this one the masking must be kept, but
it was done too early.

Cc: qemu-stable@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 
2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit b5a9de3259f4c791bde2faff086dd5737625e41e)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: 2bd4d27aa5c45f67437545789c9f7a4976f58853
      
https://github.com/qemu/qemu/commit/2bd4d27aa5c45f67437545789c9f7a4976f58853
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M tests/vm/openbsd

  Log Message:
  -----------
  tests/vm: update openbsd image to 7.4

The old links are dead so even if we have the ISO cached we can't
finish the install. Update to the current stable and tweak the install
strings.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2192
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-5-alex.bennee@linaro.org>
(cherry picked from commit 8467ac75b3b7207a49a1c6c7b87f0f7d2d0cea18)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


  Commit: 4934f922ac7eaa12cb340a9abeaa6b819332235f
      
https://github.com/qemu/qemu/commit/4934f922ac7eaa12cb340a9abeaa6b819332235f
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M tests/vm/Makefile.include
    M tests/vm/basevm.py

  Log Message:
  -----------
  tests/vm: avoid re-building the VM images all the time

The main problem is that "check-venv" is a .PHONY target will always
evaluate and trigger a full re-build of the VM images. While its
tempting to drop it from the dependencies that does introduce a
breakage on freshly configured builds.

Fortunately we do have the otherwise redundant --force flag for the
script which up until now was always on. If we make the usage of
--force conditional on dependencies other than check-venv triggering
the update we can avoid the costly rebuild and still run cleanly on a
fresh checkout.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2118
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-4-alex.bennee@linaro.org>
(cherry picked from commit 151b7dba391fab64cc008a1fdba6ddcf6f8c39c8)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>


Compare: https://github.com/qemu/qemu/compare/b3edbda64a6c...4934f922ac7e

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