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[Qemu-commits] [qemu/qemu] 6e2897: Merge tag 'mips-20241031' of https://


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 6e2897: Merge tag 'mips-20241031' of https://github.com/ph...
Date: Fri, 01 Nov 2024 07:04:32 -0700

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 6e2897caeeda8776b91e10958c6c0dda732b0d81
      
https://github.com/qemu/qemu/commit/6e2897caeeda8776b91e10958c6c0dda732b0d81
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-11-01 (Fri, 01 Nov 2024)

  Changed paths:
    M target/mips/cpu-defs.c.inc
    M target/mips/cpu.h
    M target/mips/mips-defs.h
    M target/mips/sysemu/machine.c
    A target/mips/tcg/godson2.decode
    A target/mips/tcg/loong-ext.decode
    A target/mips/tcg/loong_translate.c
    M target/mips/tcg/meson.build
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/translate.c
    M target/mips/tcg/translate.h

  Log Message:
  -----------
  Merge tag 'mips-20241031' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Migrate missing CP0 TLB MemoryMapID register (Yongbok)
- Enable MSA ASE for mips32r6-generic (Aleksandar)
- Convert Loongson LEXT opcodes to decodetree (Philippe)
- Introduce ase_3d_available and disas_mt_available helpers (Philippe)

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# gpg: Signature made Thu 31 Oct 2024 04:29:06 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" 
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'mips-20241031' of https://github.com/philmd/qemu:
  target/mips: Remove unused CPUMIPSState::current_fpu field
  target/mips: Introduce disas_mt_available()
  target/mips: Introduce ase_3d_available() helper
  target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext
  target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
  target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
  target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
  target/mips: Convert Loongson DIV.G opcodes to decodetree
  target/mips: Convert Loongson DDIV.G opcodes to decodetree
  target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
  target/mips: Simplify Loongson MULTU.G opcode
  target/mips: Extract decode_64bit_enabled() helper
  target/mips: Enable MSA ASE for mips32r6-generic
  target/mips: Migrate TLB MemoryMapID register

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>



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