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[Qemu-commits] [qemu/qemu] c9b8a1: target/ppc: Set ctx->opcode for decod
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] c9b8a1: target/ppc: Set ctx->opcode for decode_insn32() |
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Date: |
Tue, 05 Nov 2024 02:12:10 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: c9b8a13a8841e0e23901e57e24ea98eeef16cf91
https://github.com/qemu/qemu/commit/c9b8a13a8841e0e23901e57e24ea98eeef16cf91
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Set ctx->opcode for decode_insn32()
divdu (without a dot) sometimes updates cr0, even though it shouldn't.
The reason is that gen_op_arith_divd() checks Rc(ctx->opcode), which is
not initialized. This field is initialized only for instructions that
go through decode_legacy(), and not decodetree.
There already was a similar issue fixed in commit 86e6202a57b1
("target/ppc: Make divw[u] handler method decodetree compatible.").
It's not immediately clear what else may access the uninitialized
ctx->opcode, so instead of playing whack-a-mole and changing the check
to compute_rc0, simply initialize ctx->opcode.
Cc: qemu-stable@nongnu.org
Fixes: 99082815f17f ("target/ppc: Add infrastructure for prefixed insns")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 7b4820a3e1dfba2b81f2354e7c748fc04b275dba
https://github.com/qemu/qemu/commit/7b4820a3e1dfba2b81f2354e7c748fc04b275dba
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Make divd[u] handler method decodetree compatible
This is like commit 86e6202a57b1 ("target/ppc: Make divw[u] handler
method decodetree compatible."), but for gen_op_arith_divd().
Cc: qemu-stable@nongnu.org
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 899e488650bb8bd52e1b2b44ceaae17df2e20b7f
https://github.com/qemu/qemu/commit/899e488650bb8bd52e1b2b44ceaae17df2e20b7f
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/pnv_lpc.c
M target/ppc/cpu.h
Log Message:
-----------
ppc/pnv: Fix LPC serirq routing calculation
The serirq routing table is split over two registers, the calculation
for the high irqs in the second register did not subtract the irq
offset. This was spotted by Coverity as a shift-by-negative. Fix this
and change the open-coded shifting and masking to use extract32()
function so it's less error-prone.
This went unnoticed because irqs >= 14 are not used in a standard
QEMU/OPAL boot, changing the first QEMU serial-isa irq to 14 to test
does demonstrate serial irqs aren't received, and that this change
fixes that.
Cc: qemu-stable@nongnu.org
Reported-by: Cédric Le Goater <clg@redhat.com>
Resolves: Coverity CID 1558829 (partially)
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 84416e262ea1218026a8567ed9ea31c16d77edea
https://github.com/qemu/qemu/commit/84416e262ea1218026a8567ed9ea31c16d77edea
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/pnv_lpc.c
Log Message:
-----------
ppc/pnv: Fix LPC POWER8 register sanity check
POWER8 does not have the ISA IRQ -> SERIRQ routing system of later
CPUs, instead all ISA IRQs are sent to the CPU via a single PSI
interrupt. There is a sanity check in the POWER8 case to ensure the
routing bits have not been set, because that would indicate a
programming error.
Those bits were incorrectly specified because of ppc bit numbering
fun. Coverity detected this as an always-zero expression.
Cc: qemu-stable@nongnu.org
Reported-by: Cédric Le Goater <clg@redhat.com>
Resolves: Coverity CID 1558829 (partially)
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 0324d236d2918c18a9ad4a1081b1083965a1433b
https://github.com/qemu/qemu/commit/0324d236d2918c18a9ad4a1081b1083965a1433b
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/misc_helper.c
Log Message:
-----------
target/ppc: Fix mtDPDES targeting SMT siblings
A typo in the loop over SMT threads to set irq level for doorbells
when storing to DPDES meant everything was aimed at the CPU executing
the instruction.
Cc: qemu-stable@nongnu.org
Fixes: d24e80b2ae ("target/ppc: Add msgsnd/p and DPDES SMT support")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c5747965afca017e27a475082126594e8306c766
https://github.com/qemu/qemu/commit/c5747965afca017e27a475082126594e8306c766
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: PMIs are level triggered
In Book-S / Power processors, the performance monitor interrupts are
driven by the MMCR0[PMAO] bit, which is level triggered and not cleared
by the interrupt.
Others may have different performance monitor architecture, but none of
those are implemented by QEMU.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 06229545f55abfc0aebcbc493f97247ed7ed278f
https://github.com/qemu/qemu/commit/06229545f55abfc0aebcbc493f97247ed7ed278f
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix doorbell delivery to threads in powersave
Doorbell exceptions are not not cleared when they cause a wake from
powersave state, only when they take the corresponding interrupt.
The sreset-on-wake logic must avoid clearing the interrupt in this
case.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 87de77f6aeba4e38d123f7541cfdae7b124f6a02
https://github.com/qemu/qemu/commit/87de77f6aeba4e38d123f7541cfdae7b124f6a02
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Fix HFSCR facility checks
The HFSCR defines were being encoded as bit masks, but the users
expect (and analogous FSCR defines are) bit numbers.
Cc: qemu-stable@nongnu.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: fdd9cf281d6c07c23f620d14896f97de6c4356b9
https://github.com/qemu/qemu/commit/fdd9cf281d6c07c23f620d14896f97de6c4356b9
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/mmu-hash64.c
Log Message:
-----------
target/ppc: Fix VRMA to not check virtual page class key protection
Hash virtual real mode addressing is defined by the architecture
to not perform virtual page class key protection checks.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: ddd2a060a0da41000ddca31e329ab1d54e37fedb
https://github.com/qemu/qemu/commit/ddd2a060a0da41000ddca31e329ab1d54e37fedb
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/pnv_adu.c
Log Message:
-----------
ppc/pnv: ADU fix possible buffer overrun with invalid size
The ADU LPC transfer-size field is 7 bits, but the supported sizes for
LPC access via ADU appear to be 1, 2, 4, 8. The data buffer could
overrun if firmware set an invalid size field, so add checks to reject
them with a message.
Cc: qemu-stable@nongnu.org
Reported-by: Cédric Le Goater <clg@redhat.com>
Resolves: Coverity CID 1558830
Fixes: 24bd283bccb33 ("ppc/pnv: Implement ADU access to LPC space")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 3cde4c31ebe9fdfeca2d824a0036d04bec285301
https://github.com/qemu/qemu/commit/3cde4c31ebe9fdfeca2d824a0036d04bec285301
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Cover PowerPC SPI model in PowerNV section
It is unfair to let the PowerNV SPI model to the SSI
maintainers. Also include the PowerNV ones.
Fixes: 29318db133 ("hw/ssi: Add SPI model")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 65f53702d2e4bd045ce16ca874469cdd1e1ef4e4
https://github.com/qemu/qemu/commit/65f53702d2e4bd045ce16ca874469cdd1e1ef4e4
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ssi/pnv_spi.c
Log Message:
-----------
hw/ssi/pnv_spi: Match _xfer_buffer_free() with _xfer_buffer_new()
pnv_spi_xfer_buffer_new() allocates %payload using g_malloc0(),
and pnv_spi_xfer_buffer_write_ptr() allocates %payload->data
using g_realloc(). Use the API equivalent g_free() to release
the buffers.
Cc: qemu-stable@nongnu.org
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 3feabc18ad4d4bdc178a205b986353a54dbfcf20
https://github.com/qemu/qemu/commit/3feabc18ad4d4bdc178a205b986353a54dbfcf20
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ssi/pnv_spi.c
Log Message:
-----------
hw/ssi/pnv_spi: Return early in transfer()
Return early to simplify next commit.
No logical change intended.
Cc: qemu-stable@nongnu.org
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 031324472eee57bce9bd4a0231aa9b137494d8a1
https://github.com/qemu/qemu/commit/031324472eee57bce9bd4a0231aa9b137494d8a1
Author: Chalapathi V <chalapathi.v@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ssi/pnv_spi.c
Log Message:
-----------
hw/ssi/pnv_spi: Fixes Coverity CID 1558831
In this commit the following coverity scan defect has been fixed
CID 1558831: Resource leaks (RESOURCE_LEAK)
Variable "rsp_payload" going out of scope leaks the storage it
points to.
Cc: qemu-stable@nongnu.org
Fixes: Coverity CID 1558831
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Fixes: b4cb930e40 ("hw/ssi: Extend SPI model")
[PMD: Rebased on previous commit (returning earlier)]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: ddf4dd46e5c31bd223f2e867f2cae43bfd41dfb9
https://github.com/qemu/qemu/commit/ddf4dd46e5c31bd223f2e867f2cae43bfd41dfb9
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M tests/tcg/ppc64/Makefile.target
Log Message:
-----------
tests/tcg: Replace -mpower8-vector with -mcpu=power8
[1] deprecated -mpower8-vector, resulting in:
powerpc64-linux-gnu-gcc: warning: switch '-mpower8-vector' is no longer
supported
qemu/tests/tcg/ppc64/vsx_f2i_nan.c:4:15: error: expected ';' before 'float'
4 | typedef vector float vsx_float32_vec_t;
| ^~~~~~
Use -mcpu=power8 instead. In order to properly verify that this works,
one needs a big-endian (the minimum supported CPU for 64-bit
little-endian is power8 anyway) GCC configured with --enable-checking
(see GCC commit e154242724b0 ("[RS6000] Don't pass -many to the
assembler").
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109987
Cc: qemu-stable@nongnu.org
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: f10827a845bbbb0354617cc1a69e95e4c1eb18ce
https://github.com/qemu/qemu/commit/f10827a845bbbb0354617cc1a69e95e4c1eb18ce
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/ppc.c
Log Message:
-----------
hw/ppc: fix decrementer with BookE timers
The BookE decrementer stops at 0, meaning that it won't decremented
towards "negative" values. However, the current logic is inverted: decr
is updated solely when the resulting value would be negative.
Signed-off-by: Clément Chigot <chigot@adacore.com>
Fixes: 8e0a5ac87800 ("hw/ppc: Avoid decrementer rounding errors")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: a6b7325305e28a3e0169de44fe5936c485d3a8d5
https://github.com/qemu/qemu/commit/a6b7325305e28a3e0169de44fe5936c485d3a8d5
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/core/machine.c
M hw/ppc/spapr.c
M include/hw/boards.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.1
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.1 specific code with this patch for now.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 6e3d3578d7734d4a80d2d0342e588b23245d7253
https://github.com/qemu/qemu/commit/6e3d3578d7734d4a80d2d0342e588b23245d7253
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/core/machine.c
M hw/ppc/spapr.c
M include/hw/boards.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.2
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.2 specific code with this patch for now.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: b89c746c22525b6ea077f4c53d858e88742e2c62
https://github.com/qemu/qemu/commit/b89c746c22525b6ea077f4c53d858e88742e2c62
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/core/machine.c
M hw/ppc/spapr.c
M hw/ppc/spapr_pci.c
M include/hw/boards.h
M include/hw/pci-host/spapr.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.3
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.3 specific code with this patch for now.
While at it, also remove the dynamic-reconfiguration option which was
introduced to disable it by default for legacy machines until pseries-2.3.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c447bb1ad4ead9ca8620f468b0324a338877f6bf
https://github.com/qemu/qemu/commit/c447bb1ad4ead9ca8620f468b0324a338877f6bf
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.4
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.4 specific code with this patch for now.
While at it, also remove SpaprMachineClass::dr_lmb_enabled which is
now turned useless.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 615ab788a56c1e9b9f2076143153baf2f8df9adb
https://github.com/qemu/qemu/commit/615ab788a56c1e9b9f2076143153baf2f8df9adb
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.5
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.5 specific code with this patch for now.
Also drop sPAPRMachineClass::use_ohci_by_default which is now useless.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 73700ec309a6ada693db6768f34d49adfedb4085
https://github.com/qemu/qemu/commit/73700ec309a6ada693db6768f34d49adfedb4085
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.6
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.6 specific code with this patch for now.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 445d3facffe82788b880107c0849dab9505b33d9
https://github.com/qemu/qemu/commit/445d3facffe82788b880107c0849dab9505b33d9
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/machine.c
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.7
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.7 specific code with this patch for now.
While at it, also remove pre-2.8-migration and pci/mmio hacks introduced
for backward compatibility.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 4ca656075ddb929ca24d2fe804f2f9f1646d09eb
https://github.com/qemu/qemu/commit/4ca656075ddb929ca24d2fe804f2f9f1646d09eb
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.8
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.8 specific code with this patch for now.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 24ee9229fe315609edd4c89beb21d391d9a3d27d
https://github.com/qemu/qemu/commit/24ee9229fe315609edd4c89beb21d391d9a3d27d
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
M migration/savevm.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/machine.c
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.9
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.9 specific code with this patch for now.
While at it, also remove the pre-2.10 migration hacks which now become
obsolete.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 4bc0d3dc7b177adb96af3c46d82b82a405645286
https://github.com/qemu/qemu/commit/4bc0d3dc7b177adb96af3c46d82b82a405645286
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.10
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.10 specific code with this patch for now.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 28f9f87ec418cefac3c6eca35ee48747a12be424
https://github.com/qemu/qemu/commit/28f9f87ec418cefac3c6eca35ee48747a12be424
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.11
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.11 specific code with this patch.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 74801c0537bca918a4193bb2a62218a62e73a2ac
https://github.com/qemu/qemu/commit/74801c0537bca918a4193bb2a62218a62e73a2ac
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.12-sxxm
Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated
with reasons mentioned in its commit log.
Removing pseries-2.12-sxxm specific code with this patch.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c1a13064e3371b6ff2d8204a105a693c659afaf8
https://github.com/qemu/qemu/commit/c1a13064e3371b6ff2d8204a105a693c659afaf8
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M docs/about/deprecated.rst
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M include/hw/ppc/spapr_cpu_core.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/machine.c
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-2.12
Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated
with reasons mentioned in its commit log.
Removing pseries-2.12 specific code with this patch.
While at it, also remove pre-3.0-migration hacks introduced for backward
compatibility which are now turned useless.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: f41e7f7694b34e710b4d78947825734f0727683a
https://github.com/qemu/qemu/commit/f41e7f7694b34e710b4d78947825734f0727683a
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/cpu_init.c
A target/ppc/cpu_init.h
Log Message:
-----------
target/ppc: Reduce code duplication across Power9/10 init code
Power9/10 initialization code consists of a lot of logical OR of
various flag bits as supported by respective Power platform during its
initialization, most of which is duplicated and only selected bits are
added or removed as needed with each new platform support being added.
Remove the duplicate code and share using common macros.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
[adityag: renamed many POWERPC_* flags to PPC_* flags, checkpatch fixes]
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c0b2f0dd6ba71cc4e31d92eb0f8571a4b37d3853
https://github.com/qemu/qemu/commit/c0b2f0dd6ba71cc4e31d92eb0f8571a4b37d3853
Author: Aditya Gupta <adityag@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr'
Introduce 'PnvChipClass::spapr_logical_pvr' to know corresponding logical
PVR of a PowerPC CPU.
This helps to have a one-to-one mapping between PVR and logical PVR for
a CPU, and used in a later commit to handle cases where PCR of two
generations of Power chip is same, which causes regressions with
compat-mode.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: ac0fbbb2d02bc68b3c0bbc873e40dc0d75e71f4d
https://github.com/qemu/qemu/commit/ac0fbbb2d02bc68b3c0bbc873e40dc0d75e71f4d
Author: Aditya Gupta <adityag@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/compat.c
Log Message:
-----------
target/ppc: Fix regression due to Power10 and Power11 having same PCR
Power11 has the same PCR (Processor Compatibility Register) value, as
Power10.
Due to this, QEMU considers Power11 as a valid compat-mode for Power10,
ie. earlier it was possible to run QEMU with
'-M pseries,max-compat-mode=power11 --cpu power10'
Same PCR also introduced a regression where `-M pseries --cpu power10`
boots as Power11 (ie. logical PVR is of Power11, even though PVR is
Power10). The regression was due to 'do_client_architecture_support'
checking for valid compat modes and finding Power11 to be a valid compat
mode for Power10 (it happens even without passing 'max-compat-mode'
explicitly).
Fix compat-mode issue and regression, by ensuring a future Power
processor (with a higher logical_pvr value, eg. P11) cannot be valid
compat-mode for an older Power processor (eg. P10)
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c0d964076c3e7fe75ea981d34cbf84612ddde663
https://github.com/qemu/qemu/commit/c0d964076c3e7fe75ea981d34cbf84612ddde663
Author: Aditya Gupta <adityag@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/compat.c
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/cpu_init.h
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Add Power11 DD2.0 processor
Add CPU target code to add support for new Power11 Processor.
Power11 core is same as Power10, hence reuse functions defined for
Power10.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 273db89bcaf42102580a7994fdf7f0651e35092c
https://github.com/qemu/qemu/commit/273db89bcaf42102580a7994fdf7f0651e35092c
Author: Aditya Gupta <adityag@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M docs/system/ppc/pseries.rst
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
ppc/pseries: Add Power11 cpu type
Add sPAPR CPU Core definition for Power11
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 2bbddc08bc1d7046b58880454e3278530f825885
https://github.com/qemu/qemu/commit/2bbddc08bc1d7046b58880454e3278530f825885
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: use locally stored msr and avoid indirect access
hreg_compute_hflags_value already stores msr locally to be used in most
of the logic in the routine however some instances are still using
env->msr which is unnecessary. Use locally stored value as available.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 052af14ef26631b5d7a5549797abeacb42b4db8d
https://github.com/qemu/qemu/commit/052af14ef26631b5d7a5549797abeacb42b4db8d
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: optimize hreg_compute_pmu_hflags_value
Cache env->spr[SPR_POWER_MMCR0] in a local variable as used in multiple
conditions to avoid multiple indirect accesses.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 7e806070f8af07a92af6ee5bf1fa6308f91517e5
https://github.com/qemu/qemu/commit/7e806070f8af07a92af6ee5bf1fa6308f91517e5
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: optimize hreg_compute_pmu_hflags_value
The second if-condition can be true only if the first one above is true.
Enclose the latter into the former to avoid un-necessary check if first
condition fails.
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 2a05a63c1dc9698ffbd8f704772018e07853c082
https://github.com/qemu/qemu/commit/2a05a63c1dc9698ffbd8f704772018e07853c082
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: optimize p9 exception handling routines
Currently, p9 exception handling has multiple if-condition checks where
it does an indirect access to pending_interrupts and LPCR via env.
Pass the values during entry to avoid multiple indirect accesses.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 37e62398ab1deb5cbf425cca1d43c85f0fcb986c
https://github.com/qemu/qemu/commit/37e62398ab1deb5cbf425cca1d43c85f0fcb986c
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: optimize p8 exception handling routines
Most of the p8 exception handling accesses env->pending_interrupts and
env->spr[SPR_LPCR] at multiple places. Passing it directly as local
variables simplifies the code and avoids multiple indirect accesses.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 085cc364969ea62fc51ff604394364fbdac2243f
https://github.com/qemu/qemu/commit/085cc364969ea62fc51ff604394364fbdac2243f
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: optimize p7 exception handling routines
Like p8 and p9, simplifying p7 exception handling rotuines to avoid
un-necessary multiple indirect accesses to env->pending_interrupts and
env->spr[SPR_LPCR].
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: bb547c4c457600197f351de68499f845f2a1fef4
https://github.com/qemu/qemu/commit/bb547c4c457600197f351de68499f845f2a1fef4
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: simplify var usage in ppc_next_unmasked_interrupt
As previously done for arch specific handlers, simplify var usage in
ppc_next_unmasked_interrupt by caching the env->pending_interrupts and
env->spr[SPR_LPCR] in local vars and using it later at multiple places.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 8bbf0cff8c19f69825a055a8d2a9aa049d23fb85
https://github.com/qemu/qemu/commit/8bbf0cff8c19f69825a055a8d2a9aa049d23fb85
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: combine multiple ail checks into one
ppc_excp_apply_ail has multiple if-checks for ail which is un-necessary.
Combine them as appropriate.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 57ff60c1c2fbf21dbe81873dfb440edde15354b4
https://github.com/qemu/qemu/commit/57ff60c1c2fbf21dbe81873dfb440edde15354b4
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: reduce duplicate code between init_proc_POWER{9, 10}
Historically, the registration of sprs have been inherited alongwith
every new Power arch support being added leading to a lot of code
duplication. It's time to do necessary cleanups now to avoid further
duplication with newer arch support being added.
Signed-off-by: Harsh Prateek Bora <harshb@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 1d7e6318afcf060f4cd6ae3681d29a6cddf294ff
https://github.com/qemu/qemu/commit/1d7e6318afcf060f4cd6ae3681d29a6cddf294ff
Author: Amit Machhiwal <amachhiw@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr_nested.c
M include/hw/ppc/spapr_nested.h
Log Message:
-----------
spapr: nested: Add support for DPDES SPR in GSB for TCG L0
The DPDES support for doorbell emulation and handling for KVM on PAPR
guests was added in Linux via [1]. Subsequently, a new GSB (Guest State
Buffer) element for DPDES was added in Linux; the same has been missing
in TCG L0 implementation. Add support for DPDES register's APIv2 GSB
element and required handling in `spapr_nested.c`.
Currently, booting a KVM guest inside a QEMU TCG guest fails with the
following crash. The crash occurs while handling the GUEST_RUN_VCPU
hcall made in TCG L0. In the hcall handling path, map_and_getset_state()
calls getset_state(), which, in turn, calls guest_state_request_check()
to validate the GSR (Guest State Request) elements. During this process,
guest_state_request_check() iterates over the GSR elements and receives
a NULL return code from guest_state_element_type_find() for the type
variable corresponding to the DPDES register's elemetn ID (which was
unknown to TCG L0). Subsequently, getset_state() returns H_P3,
ultimately leading to the hcall failure and causing the KVM guest to
crash.
KVM: unknown exit, hardware reason ffffffffffffffea
[ ... KVM register dump ... ]
Fix this by adding the required support in TCG L0 implementation of
APIv2.
[1] https://lore.kernel.org/all/20240605113913.83715-1-gautam@linux.ibm.com/
Fixes: 4a575f9a0567 ("spapr: nested: Initialize the GSB elements lookup table.")
Suggested-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 6fb6f3096a3c417c8fe1eaaa4e80b230d19ff93d
https://github.com/qemu/qemu/commit/6fb6f3096a3c417c8fe1eaaa4e80b230d19ff93d
Author: Amit Machhiwal <amachhiw@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/spapr_nested.c
M include/hw/ppc/spapr_nested.h
Log Message:
-----------
spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0
The Power11 architected and raw mode support in Linux was merged via [1]
and the corresponding support in QEMU is waiting to be added by [2]
which in V6 currently.
Add the Power11 capabilities and the required handling in TCG L0
implementation of the "Nested PAPR API".
Note: This patch is based on [2].
[1] https://lore.kernel.org/all/20240221044623.1598642-1-mpe@ellerman.id.au/
[2] https://lore.kernel.org/all/20240731055022.696051-1-adityag@linux.ibm.com/
Signed-off-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 889c5c4c7a32be298aa499a246dbfd0c5fea8a74
https://github.com/qemu/qemu/commit/889c5c4c7a32be298aa499a246dbfd0c5fea8a74
Author: Aditya Gupta <adityag@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
hw/ppc: Implement -dtb support for PowerNV
Currently any device tree passed with -dtb option in QEMU, was ignored
by the PowerNV code.
Read and pass the passed -dtb to the kernel, thus enabling easier
debugging with custom DTBs.
The existing behaviour when -dtb is 'not' passed, is preserved as-is.
But when a '-dtb' is passed, it completely overrides any dtb nodes or
changes QEMU might have done, such as '-append' arguments to the kernel
(which are mentioned in /chosen/bootargs in the dtb), hence add warning
when -dtb is being used
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 07f2770503e24889720028ddf9ef54788ddf3b6d
https://github.com/qemu/qemu/commit/07f2770503e24889720028ddf9ef54788ddf3b6d
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/spapr_xive_kvm.c
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Fix ESB length overflow on 32-bit hosts
The length of this region can be > 32-bits, which overflows size_t on
32-bit hosts. Change to uint64_t.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: a53304639a4a7c57184472a942bbb8da5e8482a6
https://github.com/qemu/qemu/commit/a53304639a4a7c57184472a942bbb8da5e8482a6
Author: Michael Kowal <kowal@linux.vnet.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
pnv/xive: TIMA patch sets pre-req alignment and formatting changes
Making some pre-requisite alignment changes ahead of the following patch
sets. Making these changes now will ease the review of the patch sets.
Checkpatch wants the closing comment '*/' on a separate line, unless it is
on the same line as the starting comment '/*'.
There are also changes to prevent lines from spanning 80 columns.
Changed block of defines from:
#define A 1 /* original define comment is not
* preferred, but not flagged... */
#define B 2 /* Newly added define comment
* is flagged with a warning */
To:
#define A 1 /* original define comment is */
/* now fine, no warning... */
#define B 2 /* Newly added define comment */
/* is fine... */
Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: b9deafe7bf463fb7c7d7ee713774bfaf785eeb87
https://github.com/qemu/qemu/commit/b9deafe7bf463fb7c7d7ee713774bfaf785eeb87
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
pnv/xive2: Define OGEN field in the TIMA
The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This
patch defines it.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: cebfeb9e56859bcac545a2340798e005cfde21cf
https://github.com/qemu/qemu/commit/cebfeb9e56859bcac545a2340798e005cfde21cf
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive2.h
M include/hw/ppc/xive2_regs.h
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"
Adds support for single byte writes to offset 0xC18 of the TIMA address
space. When this offset is written to, the hardware disables the OS
context and copies the current state information to the odd cache line
of the pair specified by the NVT structure indexed by the OS CAM entry.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: aa90c209bf672047947c1724b50a636a292b24b9
https://github.com/qemu/qemu/commit/aa90c209bf672047947c1724b50a636a292b24b9
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
pnv/xive2: Support for "OS LGS Push" TIMA operation
Adds support for single byte writes to offset 0x15 of the TIMA address
space. This offset holds the Logical Server Group Size (LGS) field.
The field is used to evenly distribute the interrupt load among the
members of a group, but is unused in the current implementation so we
just support the writing of the value for now.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: cfeafb0d8cdba8aa7fa3f04e28430253faf051e3
https://github.com/qemu/qemu/commit/cfeafb0d8cdba8aa7fa3f04e28430253faf051e3
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive2.c
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
ppc/xive2: Dump more NVP state with 'info pic'
The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP
belongs to a VP group.
Also, print the Reporting Cache Line address, if defined.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 76798e12dfa61ff7d7bc05a6cc831c023a8ba08c
https://github.com/qemu/qemu/commit/76798e12dfa61ff7d7bc05a6cc831c023a8ba08c
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/xive2.c
M include/hw/ppc/xive2.h
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
ppc/xive2: Dump the VP-group and crowd tables with 'info pic'
The 'info pic' HMP command dumps the state of the interrupt controller.
Add the dump of the NVG and NVC tables to its output to ease debug.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: cfe9a7f286f8db4316a25ac4471d91db8b387262
https://github.com/qemu/qemu/commit/cfe9a7f286f8db4316a25ac4471d91db8b387262
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive2.h
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/xive2: Allow 1-byte write of Target field in TIMA
When running PowerVM, the console is littered with XIVE traces regarding
invalid writes to TIMA address 0x100b6 due to a lack of support for writes
to the "TARGET" field which was added for XIVE GEN2. To fix this, we add
special op support for 1-byte writes to this field.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: f82fec6c1f3bf127eb46e811b0a529d83793381c
https://github.com/qemu/qemu/commit/f82fec6c1f3bf127eb46e811b0a529d83793381c
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/xive2: Support "Pull Thread Context to Register" operation
Adds support for single byte read of offset 0x838 of the TIMA address
space. According to the XIVE2 Specification, this causes the hardware
to atomically:
1. Read the number of bytes requested (lbz or lhz are supported).
2. Reset the valid bit of the thread context.
3. Return the number of bytes requested in step 1 to a register.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 00a7a7a548ea537f888f2f90d66155f14ff93727
https://github.com/qemu/qemu/commit/00a7a7a548ea537f888f2f90d66155f14ff93727
Author: Michael Kowal <kowal@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive2: Change context/ring specific functions to be generic
Some the functions that have been created are specific to a ring or context.
Some
of these same functions are being changed to operate on any ring/context. This
will
simplify the next patch sets that are adding additional ring/context operations.
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 81939a9211dc42479fe5fd84166a714e682c1314
https://github.com/qemu/qemu/commit/81939a9211dc42479fe5fd84166a714e682c1314
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive2.h
M include/hw/ppc/xive2_regs.h
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"
Adds support for single byte writes to offset 0xC38 of the TIMA address
space. When this offset is written to, the hardware disables the thread
context and copies the current state information to the odd cache line of
the pair specified by the NVT structure indexed by the THREAD CAM entry.
Note that this operation is almost identical to what we are already doing
for the "Pull OS Context to Odd Thread Reporting Line" operation except
that it also invalidates the Pool and Thread Contexts.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: a9bb09678a7487609769f1965a04d3a774810bda
https://github.com/qemu/qemu/commit/a9bb09678a7487609769f1965a04d3a774810bda
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
pnv/xive: Add special handling for pool targets
Hypervisor "pool" targets do not get their own interrupt line and instead
must share an interrupt line with the hypervisor "physical" targets.
This also means that the pool ring must use some of the registers from the
physical ring in the TIMA. Specifically, the NSR, PIPR and CPPR registers:
NSR = Notification Source Register
PIPR = Post Interrupt Priority Register
CPPR = Current Processor Priority Register
The NSR specifies that there is an active interrupt. The CPPR
specifies the priority of the context and the PIPR specifies the
priority of the interrupt. For an interrupt to be presented to
a context, the priority of the interrupt must be higher than the
priority of the context it is interrupting (value must be lower).
The existing code was not aware of the sharing of these registers.
This commit adds that support.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 415313931917dc217f013a2ee977a059ee36bb3f
https://github.com/qemu/qemu/commit/415313931917dc217f013a2ee977a059ee36bb3f
Author: Glenn Miles <milesg@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
pnv/xive: Update PIPR when updating CPPR
Current code was updating the PIPR inside the xive_tctx_accept() function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it updated.
Moved the update to the xive_tctx_set_cppr function which required
additional support for pool interrupts.
Fixes: cdd4de68edb6 ("ppc/xive: notify the CPU when the interrupt priority is
more privileged")
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 4598ed254549a0340875487784959ed68431d373
https://github.com/qemu/qemu/commit/4598ed254549a0340875487784959ed68431d373
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
Log Message:
-----------
pnv/xive2: TIMA support for 8-byte OS context push for PHYP
PHYP uses 8-byte writes to the 2nd doubleword of the OS context
line when dispatching an OS level virtual processor. This
support was not used by OPAL/Linux and so was never added.
Without this support, the XIVE code doesn't notice that a new
context is being pushed and fails to check for unpresented
pending interrupts for that context.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 85eed50753a4f1eb059b3e9d0a59371db9bdede6
https://github.com/qemu/qemu/commit/85eed50753a4f1eb059b3e9d0a59371db9bdede6
Author: Michael Kowal <kowal@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
pnv/xive2: TIMA CI ops using alternative offsets or byte lengths
Some of the TIMA Special CI operations perform the same operation at
alternative byte offsets and lengths. The following
xive2_tm_opertions[] table entries are missing when they exist for
other offsets/sizes and have been added:
- lwz@0x810 Pull/Invalidate O/S Context to register added
lwz@0x818 exists
ld @0x818 exists
- lwz@0x820 Pull Pool Context to register added
lwz@0x828 exists
ld @0x828 exists
- lwz@0x830 Pull Thread Context to register added
lbz@0x838 exists
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 31bfbc00d0c0dc50541f6372307a2904920a75fa
https://github.com/qemu/qemu/commit/31bfbc00d0c0dc50541f6372307a2904920a75fa
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M MAINTAINERS
M tests/qtest/meson.build
A tests/qtest/pnv-xive2-common.c
A tests/qtest/pnv-xive2-common.h
A tests/qtest/pnv-xive2-flush-sync.c
A tests/qtest/pnv-xive2-test.c
Log Message:
-----------
tests/qtest: Add XIVE tests for the powernv10 machine
These XIVE tests include:
- General interrupt IRQ tests that:
- enable and trigger an interrupt
- acknowledge the interrupt
- end of interrupt processing
- Test the Pull Thread Context to Odd Thread Reporting Line
- Test the different cache flush inject and queue sync inject operations
Co-authored-by: Frederic Barrat <fbarrat@linux.ibm.com>
Co-authored-by: Glenn Miles <milesg@linux.ibm.com>
Co-authored-by: Michael Kowal <kowal@linux.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 779a30df98a7d4875115044a8aaf0bb22c53844a
https://github.com/qemu/qemu/commit/779a30df98a7d4875115044a8aaf0bb22c53844a
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/e500.c
M hw/ppc/e500.h
M hw/ppc/ppce500_spin.c
M include/hw/ppc/ppc.h
Log Message:
-----------
hw/ppc: Consolidate e500 initial mapping creation functions
Add booke206_set_tlb() utility function and use it to replace very
similar create_initial_mapping functions in e500 machines.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: afff8800717a768c48331e4f21ba6c84710cd762
https://github.com/qemu/qemu/commit/afff8800717a768c48331e4f21ba6c84710cd762
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc_booke.c
M hw/ppc/sam460ex.c
M hw/ppc/virtex_ml507.c
M include/hw/ppc/ppc.h
Log Message:
-----------
hw/ppc: Consolidate ppc440 initial mapping creation functions
Add a utility function and use it to replace very similar
create_initial_mapping functions in 440 based machines.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 592d51803e462f57f3b0f78c074bca113b234ba5
https://github.com/qemu/qemu/commit/592d51803e462f57f3b0f78c074bca113b234ba5
Author: Cédric Le Goater <clg@redhat.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Remove myself from the PowerNV machines
It's been an amazing experience working on PowerNV systems all these
years. Now it's time for IBM to take the lead on the QEMU machine and
shape its future. I'm stepping back as the maintainer of PowerNV.
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 98a8ac1e652589b115a843b39a6b84e2e322ba08
https://github.com/qemu/qemu/commit/98a8ac1e652589b115a843b39a6b84e2e322ba08
Author: Cédric Le Goater <clg@redhat.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Remove myself from XIVE
Working on XIVE has been one of the most complex and fascinating
experiences for me. It's been a real journey, and now it's time for
IBM to take over and guide its future. I'm stepping back as the
maintainer of XIVE.
Cc: Michael Kowal <kowal@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: bd4be4d9bd20a252e677239a18b6409ecee98f56
https://github.com/qemu/qemu/commit/bd4be4d9bd20a252e677239a18b6409ecee98f56
Author: David Gibson <david@gibson.dropbear.id.au>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Remove myself as reviewer
I've now well and truly moved on from ppc and qemu maintenance. I'm
occupied with other things and am pretty much just ignoring mails on these
topics I'm CCed on. Time to remove myself.
I'm still listed as a reviewer for Device Tree, I'll keep this for now,
since I do have some interest and it's lower volume.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: deb771d8f3b3e3721d45ad51b6c3364b907ce891
https://github.com/qemu/qemu/commit/deb771d8f3b3e3721d45ad51b6c3364b907ce891
Author: Patrick Leis <venture@google.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/arm/Kconfig
Log Message:
-----------
hw/arm: enable at24c with aspeed
Enable AT24C with ASPEED in the KConfig because the boards build this
device.
Signed-off-by: Patrick Leis <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: c078298301a8c72fe12da85d94372689196628bc
https://github.com/qemu/qemu/commit/c078298301a8c72fe12da85d94372689196628bc
Author: Jan Luebbe <jlu@pengutronix.de>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/sd/sd.c
Log Message:
-----------
hw/sd/sdcard: Fix calculation of size when using eMMC boot partitions
The sd_bootpart_offset() function calculates the *runtime* offset which
changes as the guest switches between accessing the main user data area
and the boot partitions by writing to the EXT_CSD_PART_CONFIG_ACC_MASK
bits, so it shouldn't be used to calculate the main user data area size.
Instead, subtract the boot_part_size directly (twice, as there are two
identical boot partitions defined by the eMMC spec).
Suggested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Fixes: c8cb19876d3e ("hw/sd/sdcard: Support boot area in emmc image")
Tested-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Commit: ed680effe33b9d4ba5d0715a689c871f6b681bf4
https://github.com/qemu/qemu/commit/ed680effe33b9d4ba5d0715a689c871f6b681bf4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Use bsa.h for PPI definitions
Use the private peripheral interrupt definitions from bsa.h instead
of defining them locally.
Note that bsa.h defines these values as INTID values, which are all
16 greater than the PPI values that we were previously using. So we
refactor the code to use INTID-based values to match that.
This is the same thing we did in commit d40ab068c07d9 for sbsa-ref.
It removes the "same constant, different values" confusion where this
board code and bsa.h both define an ARCH_GIC_MAINT_IRQ, and allows us
to use symbolic names for the timer interrupt IDs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 1f67508c1cc0223664f566980228f5a5090ffa2f
https://github.com/qemu/qemu/commit/1f67508c1cc0223664f566980228f5a5090ffa2f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation
When calculating the index into the GIC's GPIO array for per-CPU
interrupts, we have to start with the number of SPIs. The code
currently hard-codes this to 'NUM_IRQS = 256'. However the number of
SPIs is set separately and implicitly by the value of
AST2700_MAX_IRQ, which is the number of SPIs plus 32 (since it is
what we set the GIC num-irq property to).
Define AST2700_MAX_IRQ as the total number of SPIs; this brings
AST2700 into line with AST2600, which defines AST2600_MAX_IRQ as the
number of SPIs not including the 32 internal interrupts. We can then
use AST2700_MAX_IRQ instead of the hardcoded 256.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: fc2693cc35863fa715b4f16af521081d07b2a4d1
https://github.com/qemu/qemu/commit/fc2693cc35863fa715b4f16af521081d07b2a4d1
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
aspeed/soc: Support RTC for AST2700
The RTC controller between AST2600 and AST2700 are identical. Add RTC model for
AST2700 RTC support. The RTC controller registers base address is start at
0x12C0_F000 and its alarm interrupt is connected to GICINT13.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Commit: 82a919f8f19e6bb4403c92c6cc18b4714e2524ba
https://github.com/qemu/qemu/commit/82a919f8f19e6bb4403c92c6cc18b4714e2524ba
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/timer/aspeed_timer.c
Log Message:
-----------
hw/timer/aspeed: Fix coding style
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Commit: d3d6def468ff18b387ced3de79c0339aa7c1c78d
https://github.com/qemu/qemu/commit/d3d6def468ff18b387ced3de79c0339aa7c1c78d
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/timer/aspeed_timer.c
Log Message:
-----------
hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600
According to the datasheet of AST2600 description, interrupt status set by HW
and clear to "0" by software writing "1" on the specific bit.
Therefore, if firmware set the specific bit "1" in the interrupt status
register(0x34), the specific bit of "s->irq_sts" should be cleared 0.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Fixes: fadefada4d07 ("aspeed/timer: Add support for IRQ status register on the
AST2600")
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Commit: 53b316926969d55646b5d6dd8f49e74e440a44f1
https://github.com/qemu/qemu/commit/53b316926969d55646b5d6dd8f49e74e440a44f1
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/sd/aspeed_sdhci.c
Log Message:
-----------
hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1
The size of SDHCI capabilities register is 64bits, so introduces new
Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244).
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[ clg: Fixed code alignment ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 22b3c557ffd4fb9c6c034a839b3e5b82d131123a
https://github.com/qemu/qemu/commit/22b3c557ffd4fb9c6c034a839b3e5b82d131123a
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Support create flash devices via command line for AST1030
Add a "if-statement" in aspeed_minibmc_machine_init function. If users add
"-nodefaults" in command line, the flash devices should be created by users
setting. Otherwise, the flash devices are created at machine init.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Commit: e8f3acdbb8e811d80c04c3273d8c37e41ff544e7
https://github.com/qemu/qemu/commit/e8f3acdbb8e811d80c04c3273d8c37e41ff544e7
Author: Cédric Le Goater <clg@redhat.com>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Don't set always boot properties of the emmc device
Commit e554e45b4478 ("aspeed: Tune eMMC device properties to reflect
HW strapping") added support to boot from an eMMC device by setting
the boot properties of the eMMC device. This change made the
assumption that the device always has boot areas.
However, if the machine boots from the flash device (or -kernel) and
uses an eMMC device without boot areas, support would be broken. This
impacts the ast2600-evb machine which can choose to boot from flash or
eMMC using the "boot-emmc" machine option.
To provide some flexibility for Aspeed machine users to use different
flavors of eMMC devices (with or without boot areas), do not set the
eMMC device boot properties when the machine is not configured to boot
from eMMC. However, this approach makes another assumption about eMMC
devices, namely that eMMC devices from which the machine does not boot
do not have boot areas.
A preferable alternative would be to add support for user creatable
eMMC devices and define the device boot properties on the QEMU command
line :
-blockdev node-name=emmc0,driver=file,filename=mmc-ast2600-evb.raw \
-device
emmc,bus=sdhci-bus.2,drive=emmc0,boot-partition-size=1048576,boot-config=8
This is a global change requiring more thinking. Nevertheless, in the
case of the ast2600-evb machine booting from an eMMC device and when
default devices are created, the proposed change still makes sense
since the device is required to have boot areas.
Cc: Jan Luebbe <jlu@pengutronix.de>
Fixes: e554e45b4478 ("aspeed: Tune eMMC device properties to reflect
HW strapping")
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Jan Luebbe <jlu@pengutronix.de>
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 6b829602e2f10f301ff8508f3a6850a0e913142c
https://github.com/qemu/qemu/commit/6b829602e2f10f301ff8508f3a6850a0e913142c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M MAINTAINERS
M docs/about/deprecated.rst
M docs/system/ppc/pseries.rst
M hw/core/machine.c
M hw/intc/pnv_xive2.c
M hw/intc/spapr_xive_kvm.c
M hw/intc/xics.c
M hw/intc/xive.c
M hw/intc/xive2.c
M hw/ppc/e500.c
M hw/ppc/e500.h
M hw/ppc/pnv.c
M hw/ppc/pnv_adu.c
M hw/ppc/pnv_lpc.c
M hw/ppc/ppc.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc_booke.c
M hw/ppc/ppce500_spin.c
M hw/ppc/sam460ex.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_nested.c
M hw/ppc/spapr_pci.c
M hw/ppc/virtex_ml507.c
M hw/ssi/pnv_spi.c
M include/hw/boards.h
M include/hw/pci-host/spapr.h
M include/hw/ppc/ppc.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_cpu_core.h
M include/hw/ppc/spapr_nested.h
M include/hw/ppc/xive.h
M include/hw/ppc/xive2.h
M include/hw/ppc/xive2_regs.h
M include/hw/ppc/xive_regs.h
M migration/savevm.c
M target/ppc/compat.c
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
A target/ppc/cpu_init.h
M target/ppc/excp_helper.c
M target/ppc/helper_regs.c
M target/ppc/machine.c
M target/ppc/misc_helper.c
M target/ppc/mmu-hash64.c
M target/ppc/translate.c
M tests/qtest/meson.build
A tests/qtest/pnv-xive2-common.c
A tests/qtest/pnv-xive2-common.h
A tests/qtest/pnv-xive2-flush-sync.c
A tests/qtest/pnv-xive2-test.c
M tests/tcg/ppc64/Makefile.target
Log Message:
-----------
Merge tag 'pull-ppc-for-9.2-1-20241104' of https://gitlab.com/npiggin/qemu
into staging
* Various bug fixes
* Big cleanup of deprecated machines
* Power11 support for spapr
* XIVE improvements
* Goodbye to Cedric and David as ppc reviewers, thank you both o7
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# gpg: Signature made Mon 04 Nov 2024 00:15:35 GMT
# gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
# gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE
* tag 'pull-ppc-for-9.2-1-20241104' of https://gitlab.com/npiggin/qemu: (67
commits)
MAINTAINERS: Remove myself as reviewer
MAINTAINERS: Remove myself from XIVE
MAINTAINERS: Remove myself from the PowerNV machines
hw/ppc: Consolidate ppc440 initial mapping creation functions
hw/ppc: Consolidate e500 initial mapping creation functions
tests/qtest: Add XIVE tests for the powernv10 machine
pnv/xive2: TIMA CI ops using alternative offsets or byte lengths
pnv/xive2: TIMA support for 8-byte OS context push for PHYP
pnv/xive: Update PIPR when updating CPPR
pnv/xive: Add special handling for pool targets
ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"
ppc/xive2: Change context/ring specific functions to be generic
ppc/xive2: Support "Pull Thread Context to Register" operation
ppc/xive2: Allow 1-byte write of Target field in TIMA
ppc/xive2: Dump the VP-group and crowd tables with 'info pic'
ppc/xive2: Dump more NVP state with 'info pic'
pnv/xive2: Support for "OS LGS Push" TIMA operation
ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"
pnv/xive2: Define OGEN field in the TIMA
pnv/xive: TIMA patch sets pre-req alignment and formatting changes
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9a7b0a8618b1293d589a631183e80791ad7bf552
https://github.com/qemu/qemu/commit/9a7b0a8618b1293d589a631183e80791ad7bf552
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/arm/Kconfig
M hw/arm/aspeed.c
M hw/arm/aspeed_ast27x0.c
M hw/sd/aspeed_sdhci.c
M hw/sd/sd.c
M hw/timer/aspeed_timer.c
Log Message:
-----------
Merge tag 'pull-aspeed-20241104' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Fixed eMMC size calculation
* Fixed IRQ definitions on AST2700
* Added RTC support to AST2700
* Fixed timer IRQ status on AST2600
* Improved SDHCI model with new registers
* Added -nodefaults support to AST1030
* Provided a way to use an eMMC device without boot partitions
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# gpg: Signature made Mon 04 Nov 2024 10:35:54 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20241104' of https://github.com/legoater/qemu:
aspeed: Don't set always boot properties of the emmc device
aspeed: Support create flash devices via command line for AST1030
hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1
hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600
hw/timer/aspeed: Fix coding style
aspeed/soc: Support RTC for AST2700
hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation
hw/arm/aspeed_ast27x0: Use bsa.h for PPI definitions
hw/sd/sdcard: Fix calculation of size when using eMMC boot partitions
hw/arm: enable at24c with aspeed
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/11b8920ed209...9a7b0a8618b1
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- [Qemu-commits] [qemu/qemu] c9b8a1: target/ppc: Set ctx->opcode for decode_insn32(),
Peter Maydell <=