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[Qemu-commits] [qemu/qemu] 62eb37: crypto: purge 'loaded' property that
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 62eb37: crypto: purge 'loaded' property that was not fully... |
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Date: |
Wed, 06 Nov 2024 09:34:49 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 62eb377e0a3179ff57274e096eca0102f96d0170
https://github.com/qemu/qemu/commit/62eb377e0a3179ff57274e096eca0102f96d0170
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M crypto/secret_common.c
M crypto/tlscredsanon.c
M crypto/tlscredspsk.c
M crypto/tlscredsx509.c
M docs/about/removed-features.rst
M qapi/crypto.json
Log Message:
-----------
crypto: purge 'loaded' property that was not fully removed
The 'loaded' property on TLS creds and secret objects was marked as
deprecated in 6.0.0. In 7.1.0 the deprecation info was moved into
the 'removed-features.rst' file, but the property was not actually
removed, just made read-only. This was a highly unusual practice,
so finish the long overdue removal job.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: d078da86d61cf0f188cd099bef9b7b2dcfeba5a7
https://github.com/qemu/qemu/commit/d078da86d61cf0f188cd099bef9b7b2dcfeba5a7
Author: liequan che <liequanche@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M crypto/hash-gcrypt.c
M crypto/hash-nettle.c
M crypto/hash.c
M crypto/hmac-gcrypt.c
M crypto/hmac-nettle.c
M crypto/pbkdf-gcrypt.c
M crypto/pbkdf-nettle.c
M include/crypto/hash.h
M meson.build
M qapi/crypto.json
M tests/unit/test-crypto-hash.c
M tests/unit/test-crypto-hmac.c
M tests/unit/test-crypto-pbkdf.c
Log Message:
-----------
crypto: Introduce SM3 hash hmac pbkdf algorithm
Introduce the SM3 cryptographic hash algorithm (GB/T 32905-2016).
SM3 (GB/T 32905-2016) is a cryptographic standard issued by the
Organization of State Commercial Cryptography Administration (OSCCA)
as an authorized cryptographic algorithm for use within China.
Detect the SM3 cryptographic hash algorithm and enable the feature silently
if it is available.
Signed-off-by: cheliequan <cheliequan@inspur.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: bbd40a0e316bb06e1320d71fa3be7e2f3d62c7a9
https://github.com/qemu/qemu/commit/bbd40a0e316bb06e1320d71fa3be7e2f3d62c7a9
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M crypto/hash-gcrypt.c
Log Message:
-----------
crypto: fix error check on gcry_md_open
Gcrypt does not return negative values on error, it returns non-zero
values. This caused QEMU not to detect failure to open an unsupported
hash, resulting in a later crash trying to use a NULL context.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: a7e42752324a264439bef28da3ee3e2563cf0e16
https://github.com/qemu/qemu/commit/a7e42752324a264439bef28da3ee3e2563cf0e16
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M crypto/hash-gcrypt.c
M crypto/hmac-gcrypt.c
Log Message:
-----------
crypto: perform runtime check for hash/hmac support in gcrypt
gcrypto has the ability to dynamically disable hash/hmac algorithms
at runtime, so QEMU must perform a runtime check.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 6c8cec822f153bb5e2871bdb309d90bcb750c24c
https://github.com/qemu/qemu/commit/6c8cec822f153bb5e2871bdb309d90bcb750c24c
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/microblaze/petalogix_ml605_mmu.c
M hw/microblaze/xlnx-zynqmp-pmu.c
M target/microblaze/cpu.c
Log Message:
-----------
target/microblaze: Alias CPU endianness property as 'little-endian'
Alias the 'endian' property as 'little-endian' because the 'ENDI'
bit is set when the endianness is in little order, and unset in
big order.
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20241105130431.22564-2-philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <3f61b85c-9382-4520-a1ce-5476eb16fb56@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 181b3a7bb03a9448d4f1a9c46fef1c1090586fe2
https://github.com/qemu/qemu/commit/181b3a7bb03a9448d4f1a9c46fef1c1090586fe2
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M configs/devices/microblaze-softmmu/default.mak
M configs/devices/microblazeel-softmmu/default.mak
M docs/about/deprecated.rst
M hw/microblaze/petalogix_ml605_mmu.c
M hw/microblaze/xlnx-zynqmp-pmu.c
Log Message:
-----------
hw/microblaze: Deprecate big-endian petalogix-ml605 & xlnx-zynqmp-pmu
The petalogix-ml605 machine was explicitly added as little-endian only
machine in commit 00914b7d970 ("microblaze: Add PetaLogix ml605 MMU
little-endian ref design"). Mark the big-endian version as deprecated.
When the xlnx-zynqmp-pmu machine's CPU was added in commit 133d23b3ad1
("xlnx-zynqmp-pmu: Add the CPU and memory"), its 'endianness' property
was set to %true, thus wired in little endianness.
Both machine are included in the big-endian system binary, while their
CPU is working in little-endian. Unlikely to work as it. Deprecate now
as broken config so we can remove soon.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241105130431.22564-3-philmd@linaro.org>
Commit: c36ec3a9655f53a8cb21e9465f439a90ea9f1fc7
https://github.com/qemu/qemu/commit/c36ec3a9655f53a8cb21e9465f439a90ea9f1fc7
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/microblaze/petalogix_s3adsp1800_mmu.c
Log Message:
-----------
hw/microblaze/s3adsp1800: Explicit CPU endianness
By default the machine's CPU endianness is 'big' order
('little-endian' property set to %false).
This corresponds to the default when this machine was added;
see commits 6a8b1ae2020 "microblaze: Add petalogix s3a1800dsp
MMU linux ref-design." and 72b675caacf "microblaze: Hook into
the build-system." which added:
[ "$target_cpu" = "microblaze" ] && target_bigendian=yes
Later commit 877fdc12b1a ("microblaze: Allow targeting
little-endian mb") added little-endian support, forgetting
to set the CPU endianness to little-endian. Not an issue
since this property was never used, but we will use it soon,
so explicit the endianness to get the expected behavior.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241105130431.22564-4-philmd@linaro.org>
Commit: 1311b1b6e2b2eede53d6e81a1beed9d8f18e56f4
https://github.com/qemu/qemu/commit/1311b1b6e2b2eede53d6e81a1beed9d8f18e56f4
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/microblaze/petalogix_s3adsp1800_mmu.c
Log Message:
-----------
hw/microblaze/s3adsp1800: Rename unimplemented MMIO region as xps_gpio
The machine datasheet mentions the GPIO device as 'xps_gpio'.
Rename it accordingly to easily find its documentation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241105130431.22564-5-philmd@linaro.org>
Commit: 3f976457eaf12938b5b496733bf62b4daa63c282
https://github.com/qemu/qemu/commit/3f976457eaf12938b5b496733bf62b4daa63c282
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/microblaze/petalogix_s3adsp1800_mmu.c
Log Message:
-----------
hw/microblaze/s3adsp1800: Declare machine type using DEFINE_TYPES macro
Replace DEFINE_MACHINE() by DEFINE_TYPES(), converting the
class_init() handler.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241105130431.22564-6-philmd@linaro.org>
Commit: 6e64c8ef8c15e459ef2423bc0214537bbca6c50f
https://github.com/qemu/qemu/commit/6e64c8ef8c15e459ef2423bc0214537bbca6c50f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/core/machine.c
Log Message:
-----------
hw/core/machine: Add missing 'units.h' and 'error-report.h' headers
Include the missing "qemu/units.h" to fix when refactoring code:
../hw/core/machine.c:743:34: error: use of undeclared identifier 'MiB'
743 | mc->default_ram_size = 128 * MiB;
| ^
../hw/core/machine.c:750:44: error: use of undeclared identifier 'TiB'
750 | mc->smbios_memory_device_size = 2047 * TiB;
| ^
and "qemu/error-report.h" to fix:
../hw/core/machine.c:1029:13: error: call to undeclared function
'error_report' [-Wimplicit-function-declaration]
1029 | error_report("NUMA node %" PRIu16 " is missing, use "
| ^
../hw/core/machine.c:1240:9: error: call to undeclared function 'warn_report'
[-Wimplicit-function-declaration]
1240 | warn_report("CPU model %s is deprecated -- %s",
| ^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20240930221900.59525-2-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 34230ce5a97b898a53032b958841e74fde0bdac1
https://github.com/qemu/qemu/commit/34230ce5a97b898a53032b958841e74fde0bdac1
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M include/hw/i386/topology.h
M target/i386/cpu.c
Log Message:
-----------
i386/cpu: Don't enumerate the "invalid" CPU topology level
In the follow-up change, the CPU topology enumeration will be moved to
QAPI. And considerring "invalid" should not be exposed to QAPI as an
unsettable item, so, as a preparation for future changes, remove
"invalid" level from the current CPU topology enumeration structure
and define it by a macro instead.
Due to the removal of the enumeration of "invalid", bit 0 of
CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid"
level, but will start at the SMT level. Therefore, to honor this change,
update the encoding rule for CPUID[0x1F].
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-ID: <20241101083331.340178-2-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e823ebe77d8f38b181a3c277d5dd9399748bf566
https://github.com/qemu/qemu/commit/e823ebe77d8f38b181a3c277d5dd9399748bf566
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/i386/x86-common.c
M include/hw/i386/topology.h
M qapi/machine-common.json
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
hw/core: Make CPU topology enumeration arch-agnostic
Cache topology needs to be defined based on CPU topology levels. Thus,
define CPU topology enumeration in qapi/machine.json to make it generic
for all architectures.
To match the general topology naming style, rename CPU_TOPO_LEVEL_* to
CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and
socket.
Also, enumerate additional topology levels for non-i386 arches, and add
a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work
with compatibility requirement of arch-specific cache topology models.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241101083331.340178-3-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4e88e7e3403df23a0fd7a95daad1f00da80bcf81
https://github.com/qemu/qemu/commit/4e88e7e3403df23a0fd7a95daad1f00da80bcf81
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/core/machine-smp.c
M hw/core/machine.c
M include/hw/boards.h
M qapi/machine-common.json
Log Message:
-----------
qapi/qom: Define cache enumeration and properties for machine
The x86 and ARM need to allow user to configure cache properties
(current only topology):
* For x86, the default cache topology model (of max/host CPU) does not
always match the Host's real physical cache topology. Performance can
increase when the configured virtual topology is closer to the
physical topology than a default topology would be.
* For ARM, QEMU can't get the cache topology information from the CPU
registers, then user configuration is necessary. Additionally, the
cache information is also needed for MPAM emulation (for TCG) to
build the right PPTT.
Define smp-cache related enumeration and properties in QAPI, so that
user could configure cache properties for SMP system through -machine in
the subsequent patch.
Cache enumeration (CacheLevelAndType) is implemented as the combination
of cache level (level 1/2/3) and cache type (data/instruction/unified).
Currently, separated L1 cache (L1 data cache and L1 instruction cache)
with unified higher-level cache (e.g., unified L2 and L3 caches), is the
most common cache architectures.
Therefore, enumerate the L1 D-cache, L1 I-cache, L2 cache and L3 cache
with smp-cache object to add the basic cache topology support. Other
kinds of caches (e.g., L1 unified or L2/L3 separated caches) can be
added directly into CacheLevelAndType if necessary.
Cache properties (SmpCacheProperties) currently only contains cache
topology information, and other cache properties can be added in it
if necessary.
Note, define cache topology based on CPU topology level with two
reasons:
1. In practice, a cache will always be bound to the CPU container
(either private in the CPU container or shared among multiple
containers), and CPU container is often expressed in terms of CPU
topology level.
2. The x86's cache-related CPUIDs encode cache topology based on APIC
ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV
relies on also requires CPU containers to help indicate the private
shared hierarchy of the cache. Therefore, for SMP systems, it is
natural to use the CPU topology hierarchy directly in QEMU to define
the cache topology.
With smp-cache QAPI support, add smp cache topology for machine by
parsing the smp-cache object list.
Also add the helper to access/update cache topology level of machine.
Suggested-by: Daniel P. Berrange <berrange@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-ID: <20241101083331.340178-4-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f35c0221fef864e65db7641bb041c5f913e31475
https://github.com/qemu/qemu/commit/f35c0221fef864e65db7641bb041c5f913e31475
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/core/machine-smp.c
M include/hw/boards.h
Log Message:
-----------
hw/core: Check smp cache topology support for machine
Add cache_supported flags in SMPCompatProps to allow machines to
configure various caches support.
And check the compatibility of the cache properties with the
machine support in machine_parse_smp_cache().
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-ID: <20241101083331.340178-5-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 07995a46bae9d2ec0971b435834c60a4df84b03f
https://github.com/qemu/qemu/commit/07995a46bae9d2ec0971b435834c60a4df84b03f
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/core/machine-smp.c
M include/hw/boards.h
Log Message:
-----------
hw/core: Add a helper to check the cache topology level
Currently, we have no way to expose the arch-specific default cache
model because the cache model is sometimes related to the CPU model
(e.g., i386).
Since the user might configure "default" level, any comparison with
"default" is meaningless before the machine knows the specific level
that "default" refers to.
We can only check the correctness of the cache topology after the arch
loads the user-configured cache model from MachineState.smp_cache and
consumes the special "default" level by replacing it with the specific
level.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-ID: <20241101083331.340178-6-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: c620b4ee92ed3664a3d98e0fbb0b651e19fba5b6
https://github.com/qemu/qemu/commit/c620b4ee92ed3664a3d98e0fbb0b651e19fba5b6
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc/e500: Prefer QOM cast
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-4-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 2a309354ac5decf78763c9de999bfb42c8612069
https://github.com/qemu/qemu/commit/2a309354ac5decf78763c9de999bfb42c8612069
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc/e500: Remove unused "irqs" parameter
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-5-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: b5d65592d931d07d4f4bcb915d018ec9598058b4
https://github.com/qemu/qemu/commit/b5d65592d931d07d4f4bcb915d018ec9598058b4
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc/e500: Add missing device tree properties to i2c controller node
When compiling a decompiled device tree blob created with dumpdtb, dtc complains
with:
/soc@e0000000/i2c@3000: incorrect #address-cells for I2C bus
/soc@e0000000/i2c@3000: incorrect #size-cells for I2C bus
Fix this by adding the missing device tree properties.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-6-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 6b0cc658284b24e2d6d608a8e6150aa9b6747d9f
https://github.com/qemu/qemu/commit/6b0cc658284b24e2d6d608a8e6150aa9b6747d9f
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/ppc/mpc8544_guts.c
Log Message:
-----------
hw/ppc/mpc8544_guts: Populate POR PLL ratio status register
Populate this read-only register with some arbitrary values which avoids
U-Boot's get_clocks() to hang().
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-11-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 1d97f16edb4e6ff38488194ce9cd34e67743b402
https://github.com/qemu/qemu/commit/1d97f16edb4e6ff38488194ce9cd34e67743b402
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/i2c/mpc_i2c.c
M hw/i2c/trace-events
Log Message:
-----------
hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-12-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 21b1ee7691693fc84d6d4e11a1533112f629e97a
https://github.com/qemu/qemu/commit/21b1ee7691693fc84d6d4e11a1533112f629e97a
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/i2c/mpc_i2c.c
Log Message:
-----------
hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-ID: <20241103133412.73536-13-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f03d53f9e0ac10a011957c4b3fff01ec4f620a27
https://github.com/qemu/qemu/commit/f03d53f9e0ac10a011957c4b3fff01ec4f620a27
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/pci-host/ppce500.c
Log Message:
-----------
hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define
Prefer a macro rather than a string literal when instantiaging device models.
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-14-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: ab22a14dc03a9d73479203bd1ae9c0522b8a4898
https://github.com/qemu/qemu/commit/ab22a14dc03a9d73479203bd1ae9c0522b8a4898
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/pci-host/ppce500.c
Log Message:
-----------
hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-15-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 65a12bb57246a1fcadb00b544946af0cf5ed8127
https://github.com/qemu/qemu/commit/65a12bb57246a1fcadb00b544946af0cf5ed8127
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/net/fsl_etsec/miim.c
Log Message:
-----------
hw/net/fsl_etsec/miim: Reuse MII constants
Instead of defining redundant constants and using magic numbers reuse the
existing MII constants.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-ID: <20241103133412.73536-16-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 59e0f9902425f88c7e54b40db29a72eaad73c509
https://github.com/qemu/qemu/commit/59e0f9902425f88c7e54b40db29a72eaad73c509
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/net/fsl_etsec/etsec.c
Log Message:
-----------
hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-17-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: c267da0e271947d59db9524a3e51fdfd860ef7ef
https://github.com/qemu/qemu/commit/c267da0e271947d59db9524a3e51fdfd860ef7ef
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/gpio/mpc8xxx.c
Log Message:
-----------
hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-18-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0ab117f0846f415b4eb4822e07db438375a9e210
https://github.com/qemu/qemu/commit/0ab117f0846f415b4eb4822e07db438375a9e210
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/ppc/mpc8544_guts.c
Log Message:
-----------
hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-19-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 911f4dd85b298e8c366f450129fcb62b33eb3a0c
https://github.com/qemu/qemu/commit/911f4dd85b298e8c366f450129fcb62b33eb3a0c
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/sd/sdhci.c
Log Message:
-----------
hw/sd/sdhci: Prefer DEFINE_TYPES() macro
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-21-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 2b88cd1782f9182e761f4664d243af2086e6361d
https://github.com/qemu/qemu/commit/2b88cd1782f9182e761f4664d243af2086e6361d
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/block/pflash_cfi01.c
Log Message:
-----------
hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-22-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 34965e8920ba99f80ffcd369bf3cdfbbe196fb8b
https://github.com/qemu/qemu/commit/34965e8920ba99f80ffcd369bf3cdfbbe196fb8b
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/i2c/smbus_eeprom.c
Log Message:
-----------
hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-ID: <20241103133412.73536-23-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 7a5f6bad7a139cdeec130f32af020ff21c6ef37a
https://github.com/qemu/qemu/commit/7a5f6bad7a139cdeec130f32af020ff21c6ef37a
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/rtc/ds1338.c
Log Message:
-----------
hw/rtc/ds1338: Prefer DEFINE_TYPES() macro
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-24-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 887c510daa54d6e2b8ba7c94a21c7b76ca95b24d
https://github.com/qemu/qemu/commit/887c510daa54d6e2b8ba7c94a21c7b76ca95b24d
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/usb/hcd-ehci-sysbus.c
Log Message:
-----------
hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro
The naming of the TypeInfo array is inspired by hcd-ohci-sysbus.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20241103133412.73536-25-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: d37eede7a8e6ff33d21aacb41a68e63e8ffa1d60
https://github.com/qemu/qemu/commit/d37eede7a8e6ff33d21aacb41a68e63e8ffa1d60
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/riscv/riscv-iommu.c
Log Message:
-----------
hw/riscv/iommu: fix build error with clang
Introduced in 0c54acb8243, "hw/riscv: add RISC-V IOMMU base emulation".
../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'
187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext)
| ^
D:/a/_temp/msys64/clang64/lib/clang/18/include/bmi2intrin.h:217:1: note:
previous definition is here
217 | _pext_u64(unsigned long long __X, unsigned long long __Y)
| ^
After a conversation on the mailing list, it was decided to rename and
add a comment for this function.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241104222225.1523751-1-pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 731d58b545ef66072d38b428fe0dcd1d691e364c
https://github.com/qemu/qemu/commit/731d58b545ef66072d38b428fe0dcd1d691e364c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M crypto/hash-gcrypt.c
M crypto/hash-nettle.c
M crypto/hash.c
M crypto/hmac-gcrypt.c
M crypto/hmac-nettle.c
M crypto/pbkdf-gcrypt.c
M crypto/pbkdf-nettle.c
M crypto/secret_common.c
M crypto/tlscredsanon.c
M crypto/tlscredspsk.c
M crypto/tlscredsx509.c
M docs/about/removed-features.rst
M include/crypto/hash.h
M meson.build
M qapi/crypto.json
M tests/unit/test-crypto-hash.c
M tests/unit/test-crypto-hmac.c
M tests/unit/test-crypto-pbkdf.c
Log Message:
-----------
Merge tag 'crypto-fixes-pull-request' of https://gitlab.com/berrange/qemu
into staging
* Remove deprecated 'loaded' property from crypto objects
* Fix error checking of hash function in gcrypt
* Perform runtime check for hash functions in gcrypt
* Add SM3 hash function to pbkdf
# -----BEGIN PGP SIGNATURE-----
#
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# =tzW1
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 05 Nov 2024 18:40:25 GMT
# gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full]
# gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full]
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF
* tag 'crypto-fixes-pull-request' of https://gitlab.com/berrange/qemu:
crypto: perform runtime check for hash/hmac support in gcrypt
crypto: fix error check on gcry_md_open
crypto: Introduce SM3 hash hmac pbkdf algorithm
crypto: purge 'loaded' property that was not fully removed
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 63dc36944383f70f1c7a20f6104966d8560300fa
https://github.com/qemu/qemu/commit/63dc36944383f70f1c7a20f6104966d8560300fa
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M configs/devices/microblaze-softmmu/default.mak
M configs/devices/microblazeel-softmmu/default.mak
M docs/about/deprecated.rst
M hw/block/pflash_cfi01.c
M hw/core/machine-smp.c
M hw/core/machine.c
M hw/gpio/mpc8xxx.c
M hw/i2c/mpc_i2c.c
M hw/i2c/smbus_eeprom.c
M hw/i2c/trace-events
M hw/i386/x86-common.c
M hw/microblaze/petalogix_ml605_mmu.c
M hw/microblaze/petalogix_s3adsp1800_mmu.c
M hw/microblaze/xlnx-zynqmp-pmu.c
M hw/net/fsl_etsec/etsec.c
M hw/net/fsl_etsec/miim.c
M hw/pci-host/ppce500.c
M hw/ppc/e500.c
M hw/ppc/mpc8544_guts.c
M hw/riscv/riscv-iommu.c
M hw/rtc/ds1338.c
M hw/sd/sdhci.c
M hw/usb/hcd-ehci-sysbus.c
M include/hw/boards.h
M include/hw/i386/topology.h
M qapi/machine-common.json
M target/i386/cpu.c
M target/i386/cpu.h
M target/microblaze/cpu.c
Log Message:
-----------
Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into staging
Misc HW patch queue
- Deprecate a pair of untested microblaze big-endian machines (Philippe)
- Arch-agnostic CPU topology checks at machine level (Zhao)
- Cleanups on PPC E500 (Bernhard)
- Various conversions to DEFINE_TYPES() macro (Bernhard)
- Fix RISC-V _pext_u64() name clashing (Pierrick)
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 05 Nov 2024 23:32:55 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20241105' of https://github.com/philmd/qemu: (29 commits)
hw/riscv/iommu: fix build error with clang
hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro
hw/rtc/ds1338: Prefer DEFINE_TYPES() macro
hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro
hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro
hw/sd/sdhci: Prefer DEFINE_TYPES() macro
hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro
hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro
hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro
hw/net/fsl_etsec/miim: Reuse MII constants
hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro
hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define
hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro
hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access
hw/ppc/mpc8544_guts: Populate POR PLL ratio status register
hw/ppc/e500: Add missing device tree properties to i2c controller node
hw/ppc/e500: Remove unused "irqs" parameter
hw/ppc/e500: Prefer QOM cast
hw/core: Add a helper to check the cache topology level
hw/core: Check smp cache topology support for machine
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/51d7495ed990...63dc36944383
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