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[Qemu-commits] [qemu/qemu] a0dfe5: target/arm/tcg/cpu32.c: swap ATCM and

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] a0dfe5: target/arm/tcg/cpu32.c: swap ATCM and BTCM registe...
Date: Tue, 26 Nov 2024 09:03:28 -0800 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: a0dfe58acda236ebb4ebf292b1c5980487d6d046
      
https://github.com/qemu/qemu/commit/a0dfe58acda236ebb4ebf292b1c5980487d6d046
  Author: Michael Tokarev <mjt@tls.msk.ru>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M target/arm/tcg/cpu32.c

  Log Message:
  -----------
  target/arm/tcg/cpu32.c: swap ATCM and BTCM register names

According to Cortex-R5 r1p2 manual, register with opcode2=0 is
BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
qemu labels them.  Just swap the labels to avoid confusion, -
both registers are implemented as always-zero.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241121171602.3273252-1-mjt@tls.msk.ru
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c36fb96d9da523bb706cb6140dfe8ed4276c3165
      
https://github.com/qemu/qemu/commit/c36fb96d9da523bb706cb6140dfe8ed4276c3165
  Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M docs/system/arm/emulation.rst

  Log Message:
  -----------
  docs/system/arm/emulation: mention armv9

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241122225049.1617774-2-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 75c1f8d1c981c9f9abaea00c94864ee18bf8348c
      
https://github.com/qemu/qemu/commit/75c1f8d1c981c9f9abaea00c94864ee18bf8348c
  Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M docs/system/arm/emulation.rst

  Log Message:
  -----------
  docs/system/arm/emulation: fix typo in feature name

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241122225049.1617774-3-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4fc5ec4c9c79b14abc50ec7f4827930e99302413
      
https://github.com/qemu/qemu/commit/4fc5ec4c9c79b14abc50ec7f4827930e99302413
  Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M docs/system/arm/emulation.rst

  Log Message:
  -----------
  docs/system/arm/emulation: add FEAT_SSBS2

We implemented this at the same times as FEAT_SSBS, but forgot
to list it in the documentation.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241122225049.1617774-4-pierrick.bouvier@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: improve commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2b65ea865955275bdb7e55685af04bc7cf29d236
      
https://github.com/qemu/qemu/commit/2b65ea865955275bdb7e55685af04bc7cf29d236
  Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M target/arm/tcg/cpu32.c

  Log Message:
  -----------
  target/arm/tcg/: fix typo in FEAT name

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241122225049.1617774-5-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7ddaf0ea2a5713a30bb73147b87bd76fb6421614
      
https://github.com/qemu/qemu/commit/7ddaf0ea2a5713a30bb73147b87bd76fb6421614
  Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M docs/system/arm/emulation.rst

  Log Message:
  -----------
  docs/system/arm/: add FEAT_MTE_ASYNC

We already implement FEAT_MTE_ASYNC; we just forgot to list it
in the documentation.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241122225049.1617774-6-pierrick.bouvier@linaro.org
[PMM: expand commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e8319a32271c0a8a25f2a6a55b6612629634b4cd
      
https://github.com/qemu/qemu/commit/e8319a32271c0a8a25f2a6a55b6612629634b4cd
  Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M docs/system/arm/emulation.rst

  Log Message:
  -----------
  docs/system/arm/: add FEAT_DoubleLock

We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when
the ID registers call for it.  This feature is actually one that must
*not* be implemented in v9.0, but since our documentation lists
everything we can emulate, we should include FEAT_DoubleLock in the
list.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: expand commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 23055b131072730d4a16a48ef2449cc0ad5f4ed4
      
https://github.com/qemu/qemu/commit/23055b131072730d4a16a48ef2449cc0ad5f4ed4
  Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M docs/system/arm/fby35.rst

  Log Message:
  -----------
  docs/system/arm/fby35: update link to product page

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20241122225049.1617774-8-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d8790ead55a2ef1e65332ebec63ae3c5db598942
      
https://github.com/qemu/qemu/commit/d8790ead55a2ef1e65332ebec63ae3c5db598942
  Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M docs/system/arm/aspeed.rst

  Log Message:
  -----------
  docs/system/arm/aspeed: add missing model supermicrox11spi-bmc

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Message-id: 20241122225049.1617774-13-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7cbea816187b09d4c2bf32638ee1c53a88e4c7bf
      
https://github.com/qemu/qemu/commit/7cbea816187b09d4c2bf32638ee1c53a88e4c7bf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M docs/system/arm/aspeed.rst
    M docs/system/arm/emulation.rst
    M docs/system/arm/fby35.rst
    M target/arm/tcg/cpu32.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20241126' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
 * docs/system/arm: Fix broken links and missing feature names

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# gpg: Signature made Tue 26 Nov 2024 17:01:41 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20241126' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
  docs/system/arm/fby35: update link to product page
  docs/system/arm/: add FEAT_DoubleLock
  docs/system/arm/: add FEAT_MTE_ASYNC
  target/arm/tcg/: fix typo in FEAT name
  docs/system/arm/emulation: add FEAT_SSBS2
  docs/system/arm/emulation: fix typo in feature name
  docs/system/arm/emulation: mention armv9
  target/arm/tcg/cpu32.c: swap ATCM and BTCM register names

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/ba54a7e6b868...7cbea816187b

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