[Qemu-commits] [qemu/qemu] fa416a: target/ppc: Fix non-maskable interrupt while halted

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: fa416ae6157a933ad3f7106090684759baaaf3c9
      
https://github.com/qemu/qemu/commit/fa416ae6157a933ad3f7106090684759baaaf3c9
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2024-11-27 (Wed, 27 Nov 2024)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: Fix non-maskable interrupt while halted

The ppc (pnv and spapr) NMI injection code does not go through the
asynchronous interrupt path and set a bit in env->pending_interrupts
and raise an interrupt request that the cpu_exec() loop can see.
Instead it injects the exception directly into registers.

This can lead to cpu_exec() missing that the thread has work to do,
if a NMI is injected while it was idle.

Fix this by clearing halted when injecting the interrupt. Probably
NMI injection should be reworked to use the interrupt request interface,
but this seems to work as a minimal fix.

Fixes: 3431648272d3 ("spapr: Add support for new NMI interface")
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>


  Commit: 96746f7a95a6e32d6578d417ae41dc24c564fafa
      
https://github.com/qemu/qemu/commit/96746f7a95a6e32d6578d417ae41dc24c564fafa
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2024-11-27 (Wed, 27 Nov 2024)

  Changed paths:
    M hw/ppc/pnv_core.c
    M target/ppc/cpu.h

  Log Message:
  -----------
  ppc/pnv: Fix direct controls quiesce

powernv CPUs have a set of control registers that can stop, start, and
do other things to control a thread's execution.

Using this interface to stop a thread puts it into a particular state
that can be queried, and is distinguishable from other things that might
stop the CPU (e.g., going idle, or being debugged via gdb, or stopped by
the monitor).

Add a new flag that can speficially distinguish this state where it is
stopped with control registers. This solves some hangs when rebooting
powernv machines when skiboot is modified to allow QEMU to use the CPU
control facility (that uses controls to bring all secondaries to a known
state).

Fixes: c8891955086 ("ppc/pnv: Implement POWER10 PC xscom registers for direct 
controls")
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>


  Commit: 2fc0a78a57731fda50d5b01e16fd68681900f709
      
https://github.com/qemu/qemu/commit/2fc0a78a57731fda50d5b01e16fd68681900f709
  Author: Glenn Miles <milesg@linux.ibm.com>
  Date:   2024-11-27 (Wed, 27 Nov 2024)

  Changed paths:
    M hw/ppc/pnv_core.c
    M hw/ppc/spapr_cpu_core.c
    M target/ppc/cpu.h

  Log Message:
  -----------
  target/ppc: Fix THREAD_SIBLING_FOREACH for multi-socket

The THREAD_SIBLING_FOREACH macro wasn't excluding threads from other
chips. Add chip_index field to the thread state and add a check for the
new field in the macro.

Fixes: b769d4c8f4c6 ("target/ppc: Add initial flags and helpers for SMT 
support")
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
[npiggin: set chip_index for spapr too]
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>


  Commit: 5e39814916c91485073da38f457a43bf317c1f08
      
https://github.com/qemu/qemu/commit/5e39814916c91485073da38f457a43bf317c1f08
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2024-11-27 (Wed, 27 Nov 2024)

  Changed paths:
    M hw/ppc/pnv_nest_pervasive.c

  Log Message:
  -----------
  ppc/pnv: Add xscom- prefix to pervasive-control region name

By convention, xscom regions get a xscom- prefix.

Fixes: 1adf24708bf7 ("hw/ppc: Add pnv nest pervasive common chiplet model")
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>


  Commit: e8185fdc63e1db1efba695aae568fae8a075a815
      
https://github.com/qemu/qemu/commit/e8185fdc63e1db1efba695aae568fae8a075a815
  Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
  Date:   2024-11-27 (Wed, 27 Nov 2024)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  ppc/spapr: fix drc index mismatch for partially enabled vcpus

In case when vcpus are explicitly enabled/disabled in a non-consecutive
order within a libvirt xml, it results in a drc index mismatch during
vcpu hotplug later because the existing logic uses vcpu id to derive the
corresponding drc index which is not correct. Use env->core_index to
derive a vcpu's drc index as appropriate to fix this issue.

For ex, for the given libvirt xml config:
  <vcpus>
    <vcpu id='0' enabled='yes' hotpluggable='no'/>
    <vcpu id='1' enabled='yes' hotpluggable='yes'/>
    <vcpu id='2' enabled='no' hotpluggable='yes'/>
    <vcpu id='3' enabled='yes' hotpluggable='yes'/>
    <vcpu id='4' enabled='no' hotpluggable='yes'/>
    <vcpu id='5' enabled='yes' hotpluggable='yes'/>
    <vcpu id='6' enabled='no' hotpluggable='yes'/>
    <vcpu id='7' enabled='no' hotpluggable='yes'/>
  </vcpus>

We see below error on guest console with "virsh setvcpus <domain> 5" :

pseries-hotplug-cpu: CPU with drc index 10000002 already exists

This patch fixes the issue by using correct drc index for explicitly
enabled vcpus during init.

Reported-by: Anushree Mathur <anushree.mathur@linux.vnet.ibm.com>
Tested-by: Anushree Mathur <anushree.mathur@linux.vnet.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>


  Commit: 0805136a44d39adc2467f23ac3c65e680e45d0a2
      
https://github.com/qemu/qemu/commit/0805136a44d39adc2467f23ac3c65e680e45d0a2
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2024-11-27 (Wed, 27 Nov 2024)

  Changed paths:
    M hw/pci-host/mv64361.c
    M hw/ppc/pegasos2.c

  Log Message:
  -----------
  hw/ppc/pegasos2: Fix IRQ routing from pci.0

The MV64361 has two PCI buses one of which is used for AGP on
PegasosII. So far we only emulated the PCI bus on pci.1 but some
graphics cards are only recognised by some guests when connected to
pci.0 corresponding to the AGP port. So far the interrupts were not
routed from pci.0 so this patch fixes that allowing the use of both
PCI buses. On real board only INTA and INTB are connected for AGP but
to avoid surprises we connect all 4 PCI interrupt lines so pci.0 can
be used for all PCI cards as well.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>


  Commit: 10bfa161fbcf40d74db4103a0f2402779e98d0f7
      
https://github.com/qemu/qemu/commit/10bfa161fbcf40d74db4103a0f2402779e98d0f7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M hw/pci-host/mv64361.c
    M hw/ppc/pegasos2.c
    M hw/ppc/pnv_core.c
    M hw/ppc/pnv_nest_pervasive.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M target/ppc/cpu.h
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  Merge tag 'pull-ppc-for-9.2-2-20241127' of https://gitlab.com/npiggin/qemu 
into staging

* Assorted small ppc fixes

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# gpg:                using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
# gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0  A795 67B3 0276 A862 1CAE

* tag 'pull-ppc-for-9.2-2-20241127' of https://gitlab.com/npiggin/qemu:
  hw/ppc/pegasos2: Fix IRQ routing from pci.0
  ppc/spapr: fix drc index mismatch for partially enabled vcpus
  ppc/pnv: Add xscom- prefix to pervasive-control region name
  target/ppc: Fix THREAD_SIBLING_FOREACH for multi-socket
  ppc/pnv: Fix direct controls quiesce
  target/ppc: Fix non-maskable interrupt while halted

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/7cbea816187b...10bfa161fbcf

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