[Qemu-devel] [PATCH 2/2] QEMU: Mask writes to RO bits in the command reg of PCI config space

[Amit Shah]

The Command register in the PCI config space has some read-only bits.
Any writes to those bits should be masked out.

Signed-off-by: Amit Shah <address@hidden>
---
 qemu/hw/pci.c |    3 +++
 qemu/hw/pci.h |    5 +++++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c
index 6916f4a..97dc54d 100644
--- a/qemu/hw/pci.c
+++ b/qemu/hw/pci.c
@@ -446,6 +446,9 @@ void pci_default_write_config(PCIDevice *d,
         if (can_write) {
             /* Mask out writes to reserved bits in registers */
             switch (addr) {
+           case 0x05:
+                val &= ~PCI_COMMAND_RESERVED_MASK_HI;
+                break;
             case 0x06:
                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
                 break;
diff --git a/qemu/hw/pci.h b/qemu/hw/pci.h
index a0cbdd5..f32b591 100644
--- a/qemu/hw/pci.h
+++ b/qemu/hw/pci.h
@@ -61,6 +61,11 @@ typedef struct PCIIORegion {
 
 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 
+/* Bits in the PCI Command Register (PCI 2.3 spec) */
+#define PCI_COMMAND_RESERVED   0xf800
+
+#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
+
 struct PCIDevice {
     /* PCI config space */
     uint8_t config[256];
-- 
1.5.5.1