Re: [Qemu-devel] [PATCH 5/8] target-mips: add microMIPS CPUs

[Aurelien Jarno]

On Tue, Jun 08, 2010 at 01:30:00PM -0700, Nathan Froyd wrote:
> 
> Signed-off-by: Nathan Froyd <address@hidden>
> ---
>  target-mips/translate_init.c |   61 
> ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 61 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index b79ed56..8e17f4b 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -141,6 +141,25 @@ static const mips_def_t mips_defs[] =
>          .mmu_type = MMU_TYPE_FMT,
>      },
>      {
> +        .name = "4Km-micromips",
> +        .CP0_PRid = 0x00018300,
> +        /* Config1 implemented, fixed mapping MMU,
> +           no virtual icache, uncached coherency. */
> +        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 |
> +                 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> +                 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
> +        .CP0_Config2 = MIPS_CONFIG2,
> +        .CP0_Config3 = MIPS_CONFIG3,
> +        .SYNCI_Step = 32,
> +        .CCRes = 2,
> +        .CP0_Status_rw_bitmask = 0x1258FF17,
> +        .SEGBITS = 32,
> +        .PABITS = 32,
> +        .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
> +        .mmu_type = MMU_TYPE_FMT,
> +    },
> +    {
>          .name = "4KEcR1",
>          .CP0_PRid = 0x00018400,
>          .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
> @@ -245,6 +264,25 @@ static const mips_def_t mips_defs[] =
>          .mmu_type = MMU_TYPE_R4000,
>      },
>      {
> +        .name = "24Kc-micromips",
> +        .CP0_PRid = 0x00019300,
> +        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
> +                    (MMU_TYPE_R4000 << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
> +                 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> +                 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
> +        .CP0_Config2 = MIPS_CONFIG2,
> +        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
> +        .SYNCI_Step = 32,
> +        .CCRes = 2,
> +        /* No DSP implemented. */
> +        .CP0_Status_rw_bitmask = 0x1278FF1F,
> +        .SEGBITS = 32,
> +        .PABITS = 32,
> +        .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
> +        .mmu_type = MMU_TYPE_R4000,
> +    },
> +    {
>          .name = "24Kf",
>          .CP0_PRid = 0x00019300,
>          .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
> @@ -269,6 +307,29 @@ static const mips_def_t mips_defs[] =
>          .mmu_type = MMU_TYPE_R4000,
>      },
>      {
> +        .name = "24Kf-micromips",
> +        .CP0_PRid = 0x00019300,
> +        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
> +                    (MMU_TYPE_R4000 << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
> +                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> +                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
> +        .CP0_Config2 = MIPS_CONFIG2,
> +        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
> +        .CP0_LLAddr_rw_bitmask = 0,
> +        .CP0_LLAddr_shift = 4,
> +        .SYNCI_Step = 32,
> +        .CCRes = 2,
> +        /* No DSP implemented. */
> +        .CP0_Status_rw_bitmask = 0x3678FF1F,
> +        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
> +                    (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
> +        .SEGBITS = 32,
> +        .PABITS = 32,
> +        .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
> +        .mmu_type = MMU_TYPE_R4000,
> +    },
> +    {
>          .name = "34Kf",
>          .CP0_PRid = 0x00019500,
>          .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |

None of those CPU seems to be real CPU. According to the MIPS website
(which BTW has very few details about microMIPS), the microMIPS ASE is
implemented in the M14K core, which seems to be a 4K core with R2 and
microMIPS support. Wouldn't it be better to add this one instead?

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net