Re: [Qemu-devel] [PATCH] Add privilege level check to several Cop0 instructions.

[Aurelien Jarno]

On Sat, Sep 17, 2011 at 05:05:32PM -0700, Eric Johnson wrote:
> The MIPS Architecture Verification Programs (AVPs) check privileged
> instructions for the required privilege level.  These changes are needed
> to pass the AVP suite.
> 
> Signed-off-by: Eric Johnson <address@hidden>
> ---
>  target-mips/translate.c |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index d5b1c76..d99a716 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -5940,6 +5940,8 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, 
> uint32_t opc, int rt, int
>  {
>      const char *opn = "ldst";
>  
> +    check_cp0_enabled(ctx);
> +
>      switch (opc) {
>      case OPC_MFC0:
>          if (rt == 0) {
> @@ -10125,6 +10127,7 @@ static void gen_pool32axf (CPUState *env, 
> DisasContext *ctx, int rt, int rs,
>  #ifndef CONFIG_USER_ONLY
>      case MFC0:
>      case MFC0 + 32:
> +        check_cp0_enabled(ctx);
>          if (rt == 0) {
>              /* Treat as NOP. */
>              break;
> @@ -10136,6 +10139,7 @@ static void gen_pool32axf (CPUState *env, 
> DisasContext *ctx, int rt, int rs,
>          {
>              TCGv t0 = tcg_temp_new();
>  
> +            check_cp0_enabled(ctx);
>              gen_load_gpr(t0, rt);
>              gen_mtc0(env, ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
>              tcg_temp_free(t0);
> @@ -10230,10 +10234,12 @@ static void gen_pool32axf (CPUState *env, 
> DisasContext *ctx, int rt, int rs,
>          switch (minor) {
>          case RDPGPR:
>              check_insn(env, ctx, ISA_MIPS32R2);
> +            check_cp0_enabled(ctx);
>              gen_load_srsgpr(rt, rs);
>              break;
>          case WRPGPR:
>              check_insn(env, ctx, ISA_MIPS32R2);
> +            check_cp0_enabled(ctx);
>              gen_store_srsgpr(rt, rs);
>              break;
>          default:
> @@ -10276,6 +10282,7 @@ static void gen_pool32axf (CPUState *env, 
> DisasContext *ctx, int rt, int rs,
>              {
>                  TCGv t0 = tcg_temp_new();
>  
> +                check_cp0_enabled(ctx);
>                  save_cpu_state(ctx, 1);
>                  gen_helper_di(t0);
>                  gen_store_gpr(t0, rs);
> @@ -10288,6 +10295,7 @@ static void gen_pool32axf (CPUState *env, 
> DisasContext *ctx, int rt, int rs,
>              {
>                  TCGv t0 = tcg_temp_new();
>  
> +                check_cp0_enabled(ctx);
>                  save_cpu_state(ctx, 1);
>                  gen_helper_ei(t0);
>                  gen_store_gpr(t0, rs);
> @@ -10765,6 +10773,7 @@ static void decode_micromips32_opc (CPUState *env, 
> DisasContext *ctx,
>          minor = (ctx->opcode >> 12) & 0xf;
>          switch (minor) {
>          case CACHE:
> +            check_cp0_enabled(ctx);
>              /* Treat as no-op. */
>              break;
>          case LWC2:
> @@ -12216,6 +12225,7 @@ static void decode_opc (CPUState *env, DisasContext 
> *ctx, int *is_branch)
>           break;
>      case OPC_CACHE:
>          check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
> +        check_cp0_enabled(ctx);
>          /* Treat as NOP. */
>          break;
>      case OPC_PREF:
> 
> 

Thanks, applied.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net