[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v1 06/16] target-arm: Add FAR_EL2 and 3
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-devel] [PATCH v1 06/16] target-arm: Add FAR_EL2 and 3 |
Date: |
Wed, 4 Jun 2014 04:33:46 +0200 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Tue, Jun 03, 2014 at 11:22:51AM +0100, Alex Bennée wrote:
>
> Edgar E. Iglesias writes:
>
> > From: "Edgar E. Iglesias" <address@hidden>
> >
> > Signed-off-by: Edgar E. Iglesias <address@hidden>
> > ---
> > target-arm/cpu.h | 2 +-
> > target-arm/helper.c | 6 ++++++
> > 2 files changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> > index f8ca1da..ef6a95d 100644
> > --- a/target-arm/cpu.h
> > +++ b/target-arm/cpu.h
> > @@ -187,7 +187,7 @@ typedef struct CPUARMState {
> > uint32_t ifsr_el2; /* Fault status registers. */
> > uint64_t esr_el[4];
> > uint32_t c6_region[8]; /* MPU base/size registers. */
> > - uint64_t far_el[2]; /* Fault address registers. */
> > + uint64_t far_el[4]; /* Fault address registers. */
>
> Ahh my confusion from earlier is now clear. Perhaps the two commits
> should be merged?
Hi,
The point is to have a non-functional diff and then incrementally add
the function to easy bisectability if something breaks. I don't
have a very strong opinion though, so if people insist I can squash.
Cheers,
Edgar
>
> > uint64_t par_el1; /* Translation result. */
> > uint32_t c9_insn; /* Cache lockdown registers. */
> > uint32_t c9_data;
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index da210b9..de5ee40 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -2120,6 +2120,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
> > .type = ARM_CP_NO_MIGRATE,
> > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 1,
> > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState,
> > cp15.esr_el[2]) },
> > + { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
> > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
> > + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState,
> > cp15.far_el[2]) },
> > { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
> > .type = ARM_CP_NO_MIGRATE,
> > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
> > @@ -2142,6 +2145,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
> > .type = ARM_CP_NO_MIGRATE,
> > .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 1,
> > .access = PL3_RW, .fieldoffset = offsetof(CPUARMState,
> > cp15.esr_el[3]) },
> > + { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
> > + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
> > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState,
> > cp15.far_el[3]) },
> > { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
> > .type = ARM_CP_NO_MIGRATE,
> > .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
>
> --
> Alex Bennée