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Re: [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx
From: |
Alexey Kardashevskiy |
Subject: |
Re: [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970 |
Date: |
Wed, 04 Jun 2014 15:09:29 +1000 |
User-agent: |
Mozilla/5.0 (X11; Linux i686 on x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 06/04/2014 02:32 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> +static void gen_spr_book3s_pmu_user(CPUPPCState *env)
>> +{
>> + spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UPMC1, "UPMC1",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UPMC2, "UPMC2",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UPMC3, "UPMC3",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UPMC4, "UPMC4",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_USIAR, "USIAR",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> +}
>
> The Uxxxx regs are writeable from supervisor state, aren't they? (similar
> comment as UCTRL).
Yes, they are. Will fix it.
However I did not understand the "similar comment as UCTRL" comment. UCTRL
is not writable at all.
> There is also this complicating factor in ISA 2.07 (P8) whereby the PMU Uxxxx
> SPRs are
> readable/writeable based on the state of MMCR0[PMCC] (ick!).
I'll enable writes to Uxxxx for supermode in v5 of this patch.
> I think either of these can be handled in follow up patches. I am also not
> sure that I see a
> compelling reason to model the MMCR0[PMCC] accessibility unless we actually
> start modeling the
> PMU (hard).
>
> Reviewed-by: Tom Musta <address@hidden>
>
--
Alexey
- [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 03/29] target-ppc: Refactor PPC970, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 08/29] target-ppc: Add HID4 SPR for PPC970, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 12/29] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 10/29] target-ppc: Remove check_pow_970FX, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers, Alexey Kardashevskiy, 2014/06/03