Re: [Qemu-devel] [PATCH v2] target-arm: implement PD0/PD1 bits for TTBCR

[Peter Maydell]

On 5 June 2014 11:39, Fabian Aggeler <address@hidden> wrote:
> Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
> bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
> Extensions).
>
> Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
> get_level1_table_address.
>
> Signed-off-by: Fabian Aggeler <address@hidden>

Applied to target-arm.next.

> -static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
> +static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
> +                                         uint32_t address)

(I tidied up this line so the 'uint32_t' lines up with the
'CPUARMState' on the previous line.)

thanks
-- PMM