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[Qemu-devel] [PATCH v7 1/3] target-mips: Misaligned memory accesses for
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From: |
Yongbok Kim |
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Subject: |
[Qemu-devel] [PATCH v7 1/3] target-mips: Misaligned memory accesses for R6 |
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Date: |
Mon, 1 Jun 2015 12:13:22 +0100 |
Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).
Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 39 +++++++++++++++++++++++++++------------
target-mips/translate_init.c | 2 +-
2 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index fd063a2..b13ca49 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1414,6 +1414,7 @@ typedef struct DisasContext {
int32_t CP0_Config1;
/* Routine used to access memory */
int mem_idx;
+ TCGMemOp default_tcg_memop_mask;
uint32_t hflags, saved_hflags;
int bstate;
target_ulong btarget;
@@ -2081,12 +2082,14 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_LWU:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
opn = "lwu";
break;
case OPC_LD:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
opn = "ld";
break;
@@ -2157,17 +2160,20 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
opn = "lwpc";
break;
case OPC_LW:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
opn = "lw";
break;
case OPC_LH:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+ ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
opn = "lh";
break;
case OPC_LHU:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW |
+ ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
opn = "lhu";
break;
@@ -2251,7 +2257,8 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int
rt,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_SD:
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
opn = "sd";
break;
case OPC_SDL:
@@ -2266,11 +2273,13 @@ static void gen_st (DisasContext *ctx, uint32_t opc,
int rt,
break;
#endif
case OPC_SW:
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
opn = "sw";
break;
case OPC_SH:
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+ ctx->default_tcg_memop_mask);
opn = "sh";
break;
case OPC_SB:
@@ -2347,7 +2356,8 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t
opc, int ft,
case OPC_LWC1:
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
gen_store_fpr32(fp0, ft);
tcg_temp_free_i32(fp0);
}
@@ -2357,7 +2367,8 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t
opc, int ft,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, ft);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
tcg_temp_free_i32(fp0);
}
opn = "swc1";
@@ -2365,7 +2376,8 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t
opc, int ft,
case OPC_LDC1:
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, fp0, ft);
tcg_temp_free_i64(fp0);
}
@@ -2375,7 +2387,8 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t
opc, int ft,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, ft);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
tcg_temp_free_i64(fp0);
}
opn = "sdc1";
@@ -19143,6 +19156,8 @@ gen_intermediate_code_internal(MIPSCPU *cpu,
TranslationBlock *tb,
#else
ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
#endif
+ ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
+ MO_UNALN : MO_ALIGN;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 85a65e7..ec54fef 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -607,7 +607,7 @@ static const mips_def_t mips_defs[] =
},
{
/* A generic CPU supporting MIPS64 Release 6 ISA.
- FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
+ FIXME: Support IEEE 754-2008 FP.
Eventually this should be replaced by a real CPU model. */
.name = "MIPS64R6-generic",
.CP0_PRid = 0x00010000,
--
1.7.5.4