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Re: [Qemu-devel] On x86 MMU modes
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] On x86 MMU modes |
Date: |
Wed, 3 Jun 2015 10:36:18 +0100 |
On 3 June 2015 at 10:24, Sandhya Kumar <address@hidden> wrote:
> Well, I think we can also achieve this like adding a flag in the structure
> of CPUTLBEntry.
> Am I missing something?
The point of the TLB data structure is to allow very fast access
in the common case of "TLB hit to guest RAM". If we had extra
flags to check in this code path it would slow it down. At the
moment the code only needs to look up the entry in the TLB
for the mmu_index it wants, and if it finds a hit it knows that
it is valid.
-- PMM
- [Qemu-devel] On x86 MMU modes, Sandhya Kumar, 2015/06/03
- Re: [Qemu-devel] On x86 MMU modes, Paolo Bonzini, 2015/06/03
- Re: [Qemu-devel] On x86 MMU modes, Sandhya Kumar, 2015/06/03
- Re: [Qemu-devel] On x86 MMU modes, Paolo Bonzini, 2015/06/03
- Re: [Qemu-devel] On x86 MMU modes, Sandhya Kumar, 2015/06/03
- Re: [Qemu-devel] On x86 MMU modes, Paolo Bonzini, 2015/06/03
- Re: [Qemu-devel] On x86 MMU modes, Sandhya Kumar, 2015/06/03
- Re: [Qemu-devel] On x86 MMU modes,
Peter Maydell <=
- Re: [Qemu-devel] On x86 MMU modes, Sandhya Kumar, 2015/06/06
- Re: [Qemu-devel] On x86 MMU modes, Peter Maydell, 2015/06/06
- Re: [Qemu-devel] On x86 MMU modes, Sandhya Kumar, 2015/06/07