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Re: [Qemu-devel] [PATCH v2 20/23] q35: implement SMRAM.D_LCK
From: |
Michael S. Tsirkin |
Subject: |
Re: [Qemu-devel] [PATCH v2 20/23] q35: implement SMRAM.D_LCK |
Date: |
Thu, 4 Jun 2015 14:51:54 +0200 |
On Wed, Jun 03, 2015 at 07:08:45PM +0200, Paolo Bonzini wrote:
> From: Gerd Hoffmann <address@hidden>
>
> Once the SMRAM.D_LCK bit has been set by the guest several bits in SMRAM
> and ESMRAMC become readonly until the next machine reset. Implement
> this by updating the wmask accordingly when the guest sets the lock bit.
> As the lock it itself is locked down too we don't need to worry about
> the guest clearing the lock bit.
>
> Signed-off-by: Gerd Hoffmann <address@hidden>
> Signed-off-by: Paolo Bonzini <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
> ---
> hw/pci-host/q35.c | 8 +++++++-
> include/hw/pci-host/q35.h | 3 +++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index ce101e2..2f37c29 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -268,6 +268,13 @@ static void mch_update_smram(MCHPCIState *mch)
> PCIDevice *pd = PCI_DEVICE(mch);
> bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
> MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
>
> + /* implement SMRAM.D_LCK */
> + if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) {
> + pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
> + pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK;
> + pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] =
> MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK;
> + }
> +
> memory_region_transaction_begin();
>
> if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) {
> @@ -297,7 +304,6 @@ static void mch_write_config(PCIDevice *d,
> {
> MCHPCIState *mch = MCH_PCI_DEVICE(d);
>
> - /* XXX: implement SMRAM.D_LOCK */
> pci_default_write_config(d, address, val, len);
>
> if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
> diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
> index 01b8492..113cbe8 100644
> --- a/include/hw/pci-host/q35.h
> +++ b/include/hw/pci-host/q35.h
> @@ -145,6 +145,8 @@ typedef struct Q35PCIHost {
> MCH_HOST_BRIDGE_SMRAM_D_CLS | \
> MCH_HOST_BRIDGE_SMRAM_D_LCK | \
> MCH_HOST_BRIDGE_SMRAM_G_SMRAME)
> +#define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \
> + MCH_HOST_BRIDGE_SMRAM_D_CLS
>
> #define MCH_HOST_BRIDGE_ESMRAMC 0x9e
> #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7))
> @@ -165,6 +167,7 @@ typedef struct Q35PCIHost {
> (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \
> MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \
> MCH_HOST_BRIDGE_ESMRAMC_T_EN)
> +#define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0
>
> /* D1:F0 PCIE* port*/
> #define MCH_PCIE_DEV 1
> --
> 2.4.1
>
- [Qemu-devel] [PATCH v2 14/23] hw/i386: add a separate region that tracks the SMRAME bit, (continued)
- [Qemu-devel] [PATCH v2 14/23] hw/i386: add a separate region that tracks the SMRAME bit, Paolo Bonzini, 2015/06/03
- [Qemu-devel] [PATCH v2 16/23] hw/i386: remove smram_update, Paolo Bonzini, 2015/06/03
- [Qemu-devel] [PATCH v2 15/23] target-i386: use memory API to implement SMRAM, Paolo Bonzini, 2015/06/03
- [Qemu-devel] [PATCH v2 17/23] q35: implement high SMRAM, Paolo Bonzini, 2015/06/03
- [Qemu-devel] [PATCH v2 18/23] q35: fix ESMRAMC default, Paolo Bonzini, 2015/06/03
- [Qemu-devel] [PATCH v2 20/23] q35: implement SMRAM.D_LCK, Paolo Bonzini, 2015/06/03
- Re: [Qemu-devel] [PATCH v2 20/23] q35: implement SMRAM.D_LCK,
Michael S. Tsirkin <=
- [Qemu-devel] [PATCH v2 19/23] q35: add config space wmask for SMRAM and ESMRAMC, Paolo Bonzini, 2015/06/03
- [Qemu-devel] [PATCH v2 21/23] q35: add test for SMRAM.D_LCK, Paolo Bonzini, 2015/06/03
- [Qemu-devel] [PATCH v2 22/23] q35: implement TSEG, Paolo Bonzini, 2015/06/03
- [Qemu-devel] [PATCH v2 23/23] ich9: implement SMI_LOCK, Paolo Bonzini, 2015/06/03
- Re: [Qemu-devel] [PATCH v2 00/23] SMM improvements (chipset and TCG parts), Laszlo Ersek, 2015/06/03