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Re: [Qemu-devel] [PATCH target-arm v1 2/9] arm: helper: Factor out CP re
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH target-arm v1 2/9] arm: helper: Factor out CP regs common to [pv]msa |
Date: |
Thu, 4 Jun 2015 10:54:55 -0700 |
On Mon, Jun 1, 2015 at 11:48 AM, Peter Maydell <address@hidden> wrote:
> On 1 June 2015 at 19:04, Peter Crosthwaite <address@hidden> wrote:
>> V6+ PMSA and VMSA share some common registers that are currently
>> in the VMSA definition block. Split them out into a new def that can
>> be shared to PMSA.
>>
>> Signed-off-by: Peter Crosthwaite <address@hidden>
>> ---
>> target-arm/helper.c | 15 ++++++++++-----
>> 1 file changed, 10 insertions(+), 5 deletions(-)
>>
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 1cc4993..78b6406 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -1846,7 +1846,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const
>> ARMCPRegInfo *ri,
>> raw_write(env, ri, value);
>> }
>>
>> -static const ARMCPRegInfo vmsa_cp_reginfo[] = {
>> +static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
>> { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
>> .access = PL1_RW, .type = ARM_CP_ALIAS,
>> .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
>> @@ -1856,6 +1856,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
>> .access = PL1_RW, .resetvalue = 0,
>> .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
>> offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
>> + { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
>> + .access = PL1_RW, .resetvalue = 0,
>> + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
>> + offsetof(CPUARMState, cp15.dfar_ns) } },
>
> Can you move the FAR_EL1 reginfo as well, please? They should stay
> together because they're the 32 and 64 bit versions of the same
> register.
>
Done.
> (Aside: probably there's a missing ALIAS mark.)
>
I'm not sure of the full impact of this change. Who should be the
aliaser and aliasee? I have left it out for the moment.
Regards,
Peter
> Otherwise looks OK.
>
> -- PMM
>
[Qemu-devel] [PATCH target-arm v1 3/9] target-arm/helper.c: define MPUIR register, Peter Crosthwaite, 2015/06/01
[Qemu-devel] [PATCH target-arm v1 4/9] target-arm: Add registers for PMSAv7, Peter Crosthwaite, 2015/06/01