[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v4 7/8] target-sh4: factorize fmov implementation
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v4 7/8] target-sh4: factorize fmov implementation |
Date: |
Thu, 4 Jun 2015 21:51:19 +0200 |
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-sh4/translate.c | 18 ++++++------------
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 44d0e94..5453a86 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1010,24 +1010,18 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
+ const int fr = XREG(B7_4);
+ TCGv addr = tcg_temp_new_i32();
+ tcg_gen_subi_i32(addr, REG(B11_8), 4);
if (ctx->flags & FPSCR_SZ) {
- TCGv addr = tcg_temp_new_i32();
- int fr = XREG(B7_4);
- tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEUL);
tcg_gen_subi_i32(addr, addr, 4);
tcg_gen_qemu_st_i32(cpu_fregs[fr], addr, ctx->memidx, MO_TEUL);
- tcg_gen_mov_i32(REG(B11_8), addr);
- tcg_temp_free(addr);
} else {
- TCGv addr;
- addr = tcg_temp_new_i32();
- tcg_gen_subi_i32(addr, REG(B11_8), 4);
- tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr,
- ctx->memidx, MO_TEUL);
- tcg_gen_mov_i32(REG(B11_8), addr);
- tcg_temp_free(addr);
+ tcg_gen_qemu_st_i32(cpu_fregs[fr], addr, ctx->memidx, MO_TEUL);
}
+ tcg_gen_mov_i32(REG(B11_8), addr);
+ tcg_temp_free(addr);
return;
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
CHECK_FPU_ENABLED
--
2.1.4
- [Qemu-devel] [PATCH v4 0/8] target-sh4: optimizations and cleanups, Aurelien Jarno, 2015/06/04
- [Qemu-devel] [PATCH v4 3/8] target-sh4: optimize addc using add2, Aurelien Jarno, 2015/06/04
- [Qemu-devel] [PATCH v4 8/8] target-sh4: remove dead code, Aurelien Jarno, 2015/06/04
- [Qemu-devel] [PATCH v4 4/8] target-sh4: optimize subc using sub2, Aurelien Jarno, 2015/06/04
- [Qemu-devel] [PATCH v4 5/8] target-sh4: optimize negc using add2 and sub2, Aurelien Jarno, 2015/06/04
- [Qemu-devel] [PATCH v4 6/8] target-sh4: split out Q and M from of SR and optimize div1, Aurelien Jarno, 2015/06/04
- [Qemu-devel] [PATCH v4 1/8] target-sh4: use bit number for SR constants, Aurelien Jarno, 2015/06/04
- [Qemu-devel] [PATCH v4 7/8] target-sh4: factorize fmov implementation,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v4 2/8] target-sh4: Split out T from SR, Aurelien Jarno, 2015/06/04