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[Qemu-devel] [PULL 43/62] target-i386: wake up processors that receive a
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 43/62] target-i386: wake up processors that receive an SMI |
Date: |
Fri, 5 Jun 2015 17:15:44 +0200 |
An SMI should definitely wake up a processor in halted state!
This lets OVMF boot with SMM on multiprocessor systems, although
it halts very soon after that with a "CpuIndex != BspIndex"
assertion failure.
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-i386/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 99ad551..0faca03 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -3063,7 +3063,9 @@ static bool x86_cpu_has_work(CPUState *cs)
(cs->interrupt_request & (CPU_INTERRUPT_NMI |
CPU_INTERRUPT_INIT |
CPU_INTERRUPT_SIPI |
- CPU_INTERRUPT_MCE));
+ CPU_INTERRUPT_MCE)) ||
+ ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
+ !(env->hflags & HF_SMM_MASK));
}
static Property x86_cpu_properties[] = {
--
2.4.1
- [Qemu-devel] [PULL 33/62] memory: make cpu_physical_memory_sync_dirty_bitmap() fully atomic, (continued)
- [Qemu-devel] [PULL 33/62] memory: make cpu_physical_memory_sync_dirty_bitmap() fully atomic, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 32/62] memory: replace cpu_physical_memory_reset_dirty() with test-and-clear, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 34/62] memory: use mr->ram_addr in "is this RAM?" assertions, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 35/62] icount: implement a new icount_sleep mode toggleing real-time cpu sleep, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 36/62] icount: add sleep parameter to the icount option to set icount_sleep mode, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 37/62] icount: print a warning if there is no more deadline in sleep=no mode, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 38/62] target-i386: introduce cpu_get_mem_attrs, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 40/62] target-i386: Use correct memory attributes for ioport accesses, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 41/62] target-i386: mask NMIs on entry to SMM, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 42/62] target-i386: set G=1 in SMM big real mode selectors, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 43/62] target-i386: wake up processors that receive an SMI,
Paolo Bonzini <=
- [Qemu-devel] [PULL 44/62] pflash_cfi01: change big-endian property to BIT type, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 45/62] pflash_cfi01: change to new-style MMIO accessors, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 39/62] target-i386: Use correct memory attributes for memory accesses, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 46/62] pflash_cfi01: add secure property, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 47/62] vl: allow full-blown QemuOpts syntax for -global, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 48/62] qom: add object_property_add_const_link, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 49/62] vl: run "late" notifiers immediately, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 50/62] target-i386: create a separate AddressSpace for each CPU, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 51/62] hw/i386: add a separate region that tracks the SMRAME bit, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 53/62] hw/i386: remove smram_update, Paolo Bonzini, 2015/06/05