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[Qemu-devel] [PATCH v3 1/7] target-mips: correct MFC0 for CP0.EntryLo in
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH v3 1/7] target-mips: correct MFC0 for CP0.EntryLo in MIPS64 |
Date: |
Tue, 9 Jun 2015 17:42:28 +0100 |
CP0.EntryLo bits 31:30 have to be cleared.
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index fe6bc16..668e02d 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4964,10 +4964,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
+ /* Move RI/XI fields to bits 31:30 */
TCGv tmp = tcg_temp_new();
- tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI));
- tcg_gen_shri_tl(tmp, tmp, 32);
- tcg_gen_or_tl(arg, arg, tmp);
+ tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI);
+ tcg_gen_deposit_tl(arg, arg, tmp, 30, 2);
tcg_temp_free(tmp);
}
#endif
@@ -5019,10 +5019,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
+ /* Move RI/XI fields to bits 31:30 */
TCGv tmp = tcg_temp_new();
- tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI));
- tcg_gen_shri_tl(tmp, tmp, 32);
- tcg_gen_or_tl(arg, arg, tmp);
+ tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI);
+ tcg_gen_deposit_tl(arg, arg, tmp, 30, 2);
tcg_temp_free(tmp);
}
#endif
- [Qemu-devel] [PATCH v3 0/7] target-mips: add support for large physical addresses, Leon Alrae, 2015/06/09
- [Qemu-devel] [PATCH v3 1/7] target-mips: correct MFC0 for CP0.EntryLo in MIPS64,
Leon Alrae <=
- [Qemu-devel] [PATCH v3 3/7] target-mips: support Page Frame Number Extension field, Leon Alrae, 2015/06/09
- [Qemu-devel] [PATCH v3 4/7] target-mips: add CP0.PageGrain.ELPA support, Leon Alrae, 2015/06/09
- [Qemu-devel] [PATCH v3 2/7] target-mips: extend selected CP0 registers to 64-bits in MIPS32, Leon Alrae, 2015/06/09
- [Qemu-devel] [PATCH v3 5/7] target-mips: add MTHC0 and MFHC0 instructions, Leon Alrae, 2015/06/09
- [Qemu-devel] [PATCH v3 6/7] target-mips: remove misleading comments in translate_init.c, Leon Alrae, 2015/06/09
- [Qemu-devel] [PATCH v3 7/7] target-mips: enable XPA and LPA features, Leon Alrae, 2015/06/09
- Re: [Qemu-devel] [PATCH v3 0/7] target-mips: add support for large physical addresses, Aurelien Jarno, 2015/06/11