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[Qemu-devel] [PULL 01/29] target-mips: move group of functions above gen
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 01/29] target-mips: move group of functions above gen_load_fpr32() |
Date: |
Fri, 12 Jun 2015 10:35:08 +0100 |
Move the "Tests" group of functions so that gen_load_fpr32() and
gen_store_fpr32() can use generate_exception().
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 118 ++++++++++++++++++++++++------------------------
1 file changed, 58 insertions(+), 60 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index fd063a2..c087fb5 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1557,6 +1557,64 @@ static inline void gen_store_srsgpr (int from, int to)
}
}
+/* Tests */
+static inline void gen_save_pc(target_ulong pc)
+{
+ tcg_gen_movi_tl(cpu_PC, pc);
+}
+
+static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
+{
+ LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
+ if (do_save_pc && ctx->pc != ctx->saved_pc) {
+ gen_save_pc(ctx->pc);
+ ctx->saved_pc = ctx->pc;
+ }
+ if (ctx->hflags != ctx->saved_hflags) {
+ tcg_gen_movi_i32(hflags, ctx->hflags);
+ ctx->saved_hflags = ctx->hflags;
+ switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
+ case MIPS_HFLAG_BR:
+ break;
+ case MIPS_HFLAG_BC:
+ case MIPS_HFLAG_BL:
+ case MIPS_HFLAG_B:
+ tcg_gen_movi_tl(btarget, ctx->btarget);
+ break;
+ }
+ }
+}
+
+static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
+{
+ ctx->saved_hflags = ctx->hflags;
+ switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
+ case MIPS_HFLAG_BR:
+ break;
+ case MIPS_HFLAG_BC:
+ case MIPS_HFLAG_BL:
+ case MIPS_HFLAG_B:
+ ctx->btarget = env->btarget;
+ break;
+ }
+}
+
+static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
+{
+ TCGv_i32 texcp = tcg_const_i32(excp);
+ TCGv_i32 terr = tcg_const_i32(err);
+ save_cpu_state(ctx, 1);
+ gen_helper_raise_exception_err(cpu_env, texcp, terr);
+ tcg_temp_free_i32(terr);
+ tcg_temp_free_i32(texcp);
+}
+
+static inline void generate_exception(DisasContext *ctx, int excp)
+{
+ save_cpu_state(ctx, 1);
+ gen_helper_0e0i(raise_exception, excp);
+}
+
/* Floating point register moves. */
static void gen_load_fpr32(TCGv_i32 t, int reg)
{
@@ -1626,66 +1684,6 @@ static inline int get_fp_bit (int cc)
return 23;
}
-/* Tests */
-static inline void gen_save_pc(target_ulong pc)
-{
- tcg_gen_movi_tl(cpu_PC, pc);
-}
-
-static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
-{
- LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
- if (do_save_pc && ctx->pc != ctx->saved_pc) {
- gen_save_pc(ctx->pc);
- ctx->saved_pc = ctx->pc;
- }
- if (ctx->hflags != ctx->saved_hflags) {
- tcg_gen_movi_i32(hflags, ctx->hflags);
- ctx->saved_hflags = ctx->hflags;
- switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
- case MIPS_HFLAG_BR:
- break;
- case MIPS_HFLAG_BC:
- case MIPS_HFLAG_BL:
- case MIPS_HFLAG_B:
- tcg_gen_movi_tl(btarget, ctx->btarget);
- break;
- }
- }
-}
-
-static inline void restore_cpu_state (CPUMIPSState *env, DisasContext *ctx)
-{
- ctx->saved_hflags = ctx->hflags;
- switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
- case MIPS_HFLAG_BR:
- break;
- case MIPS_HFLAG_BC:
- case MIPS_HFLAG_BL:
- case MIPS_HFLAG_B:
- ctx->btarget = env->btarget;
- break;
- }
-}
-
-static inline void
-generate_exception_err (DisasContext *ctx, int excp, int err)
-{
- TCGv_i32 texcp = tcg_const_i32(excp);
- TCGv_i32 terr = tcg_const_i32(err);
- save_cpu_state(ctx, 1);
- gen_helper_raise_exception_err(cpu_env, texcp, terr);
- tcg_temp_free_i32(terr);
- tcg_temp_free_i32(texcp);
-}
-
-static inline void
-generate_exception (DisasContext *ctx, int excp)
-{
- save_cpu_state(ctx, 1);
- gen_helper_0e0i(raise_exception, excp);
-}
-
/* Addresses computation */
static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0,
TCGv arg1)
{
--
2.1.0
- [Qemu-devel] [PULL 00/29] target-mips queue, Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 01/29] target-mips: move group of functions above gen_load_fpr32(),
Leon Alrae <=
- [Qemu-devel] [PULL 03/29] mips_malta: provide ememsize env variable to kernels, Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 05/29] softmmu: Add probe_write(), Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 04/29] target-mips: Misaligned memory accesses for R6, Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 08/29] mips jazz: compile only in 64 bit, Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 07/29] target-mips: add ERETNC instruction and Config5.LLB bit, Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 12/29] dma/rc4030: document register at offset 0x210, Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 06/29] target-mips: Misaligned memory accesses for MSA, Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 11/29] dma/rc4030: do not use old_mmio accesses, Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 09/29] dma/rc4030: create custom DMA address space, Leon Alrae, 2015/06/12
- [Qemu-devel] [PULL 15/29] net/dp8393x: always calculate proper checksums, Leon Alrae, 2015/06/12