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[Qemu-devel] [PATCH target-arm v2 03/13] arm: helper: Factor out CP regs
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v2 03/13] arm: helper: Factor out CP regs common to [pv]msa |
Date: |
Fri, 12 Jun 2015 12:10:29 -0700 |
V6+ PMSA and VMSA share some common registers that are currently
in the VMSA definition block. Split them out into a new def that can
be shared to PMSA.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
Factor out FAR_EL1 as well
target-arm/helper.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ce320ed..fa80884 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1846,7 +1846,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
raw_write(env, ri, value);
}
-static const ARMCPRegInfo vmsa_cp_reginfo[] = {
+static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_ALIAS,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
@@ -1856,6 +1856,18 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.access = PL1_RW, .resetvalue = 0,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
+ { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
+ .access = PL1_RW, .resetvalue = 0,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
+ offsetof(CPUARMState, cp15.dfar_ns) } },
+ { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
+ .resetvalue = 0, },
+ REGINFO_SENTINEL
+};
+
+static const ARMCPRegInfo vmsa_cp_reginfo[] = {
{ .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
.access = PL1_RW,
@@ -1880,14 +1892,6 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
- { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
- .resetvalue = 0, },
- { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .resetvalue = 0,
- .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
- offsetof(CPUARMState, cp15.dfar_ns) } },
REGINFO_SENTINEL
};
@@ -3349,6 +3353,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
assert(!arm_feature(env, ARM_FEATURE_V6));
define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
} else {
+ define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
--
2.4.3.3.g905f831
- [Qemu-devel] [PATCH target-arm v2 00/13] ARM Cortex R5 Support, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 01/13] arm: Do not define TLBTR in PMSA systems, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 02/13] arm: Don't add v7mp registers in MPU systems, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 03/13] arm: helper: Factor out CP regs common to [pv]msa,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v2 04/13] arm: Refactor get_phys_addr FSR return mechanism, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 05/13] arm: Implement uniprocessor with MP config, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 06/13] arm: Add has-mpu property, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 07/13] target-arm/helper.c: define MPUIR register, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 08/13] arm: helper: rename get_phys_addr_mpu, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 09/13] target-arm: Add registers for PMSAv7, Peter Crosthwaite, 2015/06/12