[Qemu-devel] [PATCH v2 00/15] target-mips: add microMIPS32 R6 Instruction Set support

[Yongbok Kim]

The patchset implements the latest microMIPS32 Release 6 Instruction Set.
However LLX, LLXE, SCX and SCXE aren't included in the patchset.

For more information, microMIPS R6 Instruction Set document is available:
MIPS Architecture for Programmers Volume II-B: microMIPS32 Instruction Set
Revision 6.01
http://www.imgtec.com/mips/architectures/mips32.asp

---
v2:
* Updated for review comment (Leon, Aurelien)
* Added signal RI exception when FIR.PS = 0 (Leon) 
* Removed an unused argument from decode_micromips32_opc()
* Reused gen_pcrel() for pc relative instructions (Leon)

Yongbok Kim (15):
  target-mips: fix {RD,WR}PGPR in microMIPS
  target-mips: add microMIPS TLBINV, TLBINVF
  target-mips: remove an unused argument
  target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP
  target-mips: rearrange gen_compute_compact_branch
  target-mips: raise RI exceptions when FIR.PS = 0
  target-mips: signal RI for removed instructions in microMIPS R6
  target-mips: add microMIPS32 R6 opcode enum
  target-mips: microMIPS32 R6 branches and jumps
  target-mips: microMIPS32 R6 POOL32A{XF} instructions
  target-mips: microMIPS32 R6 POOL32F instructions
  target-mips: microMIPS32 R6 POOL32{I,C} instructions
  target-mips: microMIPS32 R6 Major instructions
  target-mips: microMIPS32 R6 POOL16{A,C} instructions
  target-mips: add mips32r6-generic CPU definition

 target-mips/translate.c      | 2088 ++++++++++++++++++++++++++++--------------
 target-mips/translate_init.c |   37 +
 2 files changed, 1452 insertions(+), 673 deletions(-)

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1.7.5.4