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Re: [Qemu-devel] [PATCH v4 06/15] target-mips: raise RI exceptions when
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH v4 06/15] target-mips: raise RI exceptions when FIR.PS = 0 |
Date: |
Fri, 26 Jun 2015 00:06:43 +0200 |
User-agent: |
Mutt/1.5.23 (2014-03-12) |
On 2015-06-25 00:24, Yongbok Kim wrote:
> 64-bit paired-single (PS) floating point data type is optional in the
> pre-Release 6.
> It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
> (The PS data type is removed in the Release 6.)
> Loongson-2E and Loongson-2F don't have any implementation field in FCSR0(FIR)
> but do support PS data format, therefore for these cores RI will not be
> signalled regardless of PS bit.
>
> Signed-off-by: Yongbok Kim <address@hidden>
> Reviewed-by: Leon Alrae <address@hidden>
> ---
> target-mips/translate.c | 78
> +++++++++++++++++++++++++++--------------------
> 1 files changed, 45 insertions(+), 33 deletions(-)
Reviewed-by: Aurelien Jarno <address@hidden>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH v4 01/15] target-mips: fix {RD, WR}PGPR in microMIPS, (continued)
- [Qemu-devel] [PATCH v4 01/15] target-mips: fix {RD, WR}PGPR in microMIPS, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 02/15] target-mips: add microMIPS TLBINV, TLBINVF, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 03/15] target-mips: remove an unused argument, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 04/15] target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 08/15] target-mips: add microMIPS32 R6 opcode enum, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 10/15] target-mips: microMIPS32 R6 POOL32A{XF} instructions, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 05/15] target-mips: rearrange gen_compute_compact_branch, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 12/15] target-mips: microMIPS32 R6 POOL32{I, C} instructions, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 13/15] target-mips: microMIPS32 R6 Major instructions, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 06/15] target-mips: raise RI exceptions when FIR.PS = 0, Yongbok Kim, 2015/06/24
- Re: [Qemu-devel] [PATCH v4 06/15] target-mips: raise RI exceptions when FIR.PS = 0,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v4 11/15] target-mips: microMIPS32 R6 POOL32F instructions, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 15/15] target-mips: add mips32r6-generic CPU definition, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 09/15] target-mips: microMIPS32 R6 branches and jumps, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 07/15] target-mips: signal RI for removed instructions in microMIPS R6, Yongbok Kim, 2015/06/24
- [Qemu-devel] [PATCH v4 14/15] target-mips: microMIPS32 R6 POOL16{A, C} instructions, Yongbok Kim, 2015/06/24