[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 17/20] target-mips: microMIPS32 R6 POOL32{I, C} instr
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 17/20] target-mips: microMIPS32 R6 POOL32{I, C} instructions |
Date: |
Fri, 26 Jun 2015 11:25:21 +0100 |
From: Yongbok Kim <address@hidden>
Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions
Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 27 +++++++++++++++++++++------
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 1c9bfdb..1e79c5a 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -14666,9 +14666,18 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_TGEIU;
goto do_trapi;
- case TNEI:
- mips32_op = OPC_TNEI;
- goto do_trapi;
+ case TNEI: /* SYNCI */
+ if (ctx->insn_flags & ISA_MIPS32R6) {
+ /* SYNCI */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->bstate = BS_STOP;
+ } else {
+ /* TNEI */
+ mips32_op = OPC_TNEI;
+ goto do_trapi;
+ }
+ break;
case TEQI:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_TEQI;
@@ -14741,6 +14750,8 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case POOL32C:
minor = (ctx->opcode >> 12) & 0xf;
+ offset = sextract32(ctx->opcode, 0,
+ (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12);
switch (minor) {
case LWL:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
@@ -14798,23 +14809,27 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
mips32_op = OPC_LL;
goto do_ld_lr;
do_ld_lr:
- gen_ld(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12));
+ gen_ld(ctx, mips32_op, rt, rs, offset);
break;
do_st_lr:
gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12));
break;
case SC:
- gen_st_cond(ctx, OPC_SC, rt, rs, SIMM(ctx->opcode, 0, 12));
+ gen_st_cond(ctx, OPC_SC, rt, rs, offset);
break;
#if defined(TARGET_MIPS64)
case SCD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- gen_st_cond(ctx, OPC_SCD, rt, rs, SIMM(ctx->opcode, 0, 12));
+ gen_st_cond(ctx, OPC_SCD, rt, rs, offset);
break;
#endif
case PREF:
/* Treat as no-op */
+ if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
+ /* hint codes 24-31 are reserved and signal RI */
+ generate_exception(ctx, EXCP_RI);
+ }
break;
default:
MIPS_INVAL("pool32c");
--
2.1.0
- [Qemu-devel] [PULL 03/20] target-mips: remove identical code in different branch, (continued)
- [Qemu-devel] [PULL 03/20] target-mips: remove identical code in different branch, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 09/20] target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 04/20] target-mips: add Unified Hosting Interface (UHI) support, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 08/20] target-mips: remove an unused argument, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 14/20] target-mips: microMIPS32 R6 branches and jumps, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 11/20] target-mips: raise RI exceptions when FIR.PS = 0, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 13/20] target-mips: add microMIPS32 R6 opcode enum, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 15/20] target-mips: microMIPS32 R6 POOL32A{XF} instructions, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 12/20] target-mips: signal RI for removed instructions in microMIPS R6, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 10/20] target-mips: rearrange gen_compute_compact_branch, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 17/20] target-mips: microMIPS32 R6 POOL32{I, C} instructions,
Leon Alrae <=
- [Qemu-devel] [PULL 18/20] target-mips: microMIPS32 R6 Major instructions, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 19/20] target-mips: microMIPS32 R6 POOL16{A, C} instructions, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 16/20] target-mips: microMIPS32 R6 POOL32F instructions, Leon Alrae, 2015/06/26
- [Qemu-devel] [PULL 20/20] target-mips: add mips32r6-generic CPU definition, Leon Alrae, 2015/06/26
- Re: [Qemu-devel] [PULL 00/20] target-mips queue, Peter Maydell, 2015/06/26