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Re: [Qemu-devel] [PATCH v2 for-2.4 2/2] target-arm: Implement YIELD insn
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v2 for-2.4 2/2] target-arm: Implement YIELD insn to yield in ARM and Thumb translators |
Date: |
Tue, 30 Jun 2015 10:40:33 -0700 |
On Tue, Jun 30, 2015 at 6:51 AM, Peter Maydell <address@hidden> wrote:
> Implement the YIELD instruction in the ARM and Thumb translators to
> actually yield control back to the top level loop rather than being
> a simple no-op. (We already do this for A64.)
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
> ---
> target-arm/translate.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 971b6db..69ac18c 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -4080,6 +4080,10 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc,
> TCGv_i32 cpsr)
> static void gen_nop_hint(DisasContext *s, int val)
> {
> switch (val) {
> + case 1: /* yield */
> + gen_set_pc_im(s, s->pc);
> + s->is_jmp = DISAS_YIELD;
> + break;
> case 3: /* wfi */
> gen_set_pc_im(s, s->pc);
> s->is_jmp = DISAS_WFI;
> @@ -11459,6 +11463,9 @@ static inline void
> gen_intermediate_code_internal(ARMCPU *cpu,
> case DISAS_WFE:
> gen_helper_wfe(cpu_env);
> break;
> + case DISAS_YIELD:
> + gen_helper_yield(cpu_env);
> + break;
> case DISAS_SWI:
> gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
> default_exception_el(dc));
> --
> 1.9.1
>
>