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[Qemu-devel] [PATCH 7/7] target-tricore: Add ftoi and itof instructions
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 7/7] target-tricore: Add ftoi and itof instructions |
Date: |
Tue, 1 Mar 2016 17:24:28 +0100 |
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/fpu_helper.c | 46 +++++++++++++++++++++++++++++++++++++++++++++
target-tricore/helper.h | 2 ++
target-tricore/translate.c | 6 ++++++
3 files changed, 54 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index ceda415..3c09300 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -200,3 +200,49 @@ uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1,
uint32_t r2)
return result;
}
+
+uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_arg = make_float32(arg);
+ int32_t result;
+
+ f_set_flags(env);
+
+ result = float32_to_int32(f_arg, &env->fp_status);
+
+ if (float32_is_any_nan(f_arg)) {
+ env->FPU_FI = (1 << 31);
+ result = 0;
+ }
+
+ env->FPU_FS = 0;
+ if (get_float_exception_flags(&env->fp_status) & float_flag_invalid) {
+ env->FPU_FI = (1 << 31);
+ env->FPU_FS = 1;
+ }
+
+ if (get_float_exception_flags(&env->fp_status) & float_flag_inexact) {
+ env->PSW |= 1 << 26;
+ env->FPU_FS = 1;
+ }
+
+ return (uint32_t)result;
+}
+
+uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_result;
+
+ f_set_flags(env);
+
+ f_result = int32_to_float32(arg, &env->fp_status);
+
+ env->FPU_FS = 0;
+
+ if (get_float_exception_flags(&env->fp_status) & float_flag_inexact) {
+ env->PSW |= 1 << 26;
+ env->FPU_FS = 1;
+ }
+
+ return (uint32_t)f_result;
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 489530f..9333e16 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -110,6 +110,8 @@ DEF_HELPER_3(fsub, i32, env, i32, i32)
DEF_HELPER_3(fmul, i32, env, i32, i32)
DEF_HELPER_3(fdiv, i32, env, i32, i32)
DEF_HELPER_3(fcmp, i32, env, i32, i32)
+DEF_HELPER_2(ftoi, i32, env, i32)
+DEF_HELPER_2(itof, i32, env, i32)
/* dvinit */
DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index a6e5c64..30ff016 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6681,6 +6681,12 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ case OPC2_32_RR_FTOI:
+ gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
+ case OPC2_32_RR_ITOF:
+ gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
--
2.7.2
- [Qemu-devel] [PATCH 0/7] TriCore FPU patches, Bastian Koppelmann, 2016/03/01
- [Qemu-devel] [PATCH 2/7] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide, Bastian Koppelmann, 2016/03/01
- [Qemu-devel] [PATCH 7/7] target-tricore: Add ftoi and itof instructions,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 1/7] target-tricore: Add FPU infrastructure, Bastian Koppelmann, 2016/03/01
- [Qemu-devel] [PATCH 5/7] target-tricore: Add div.f instruction, Bastian Koppelmann, 2016/03/01
- [Qemu-devel] [PATCH 4/7] target-tricore: Add mul.f instruction, Bastian Koppelmann, 2016/03/01
- [Qemu-devel] [PATCH 3/7] target-tricore: add add.f/sub.f instructions, Bastian Koppelmann, 2016/03/01
- [Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction, Bastian Koppelmann, 2016/03/01