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[Qemu-devel] [PATCH 0/3] ppc: Define some more SPRs of POWER8 in QEMU to
From: |
Thomas Huth |
Subject: |
[Qemu-devel] [PATCH 0/3] ppc: Define some more SPRs of POWER8 in QEMU to fix migration |
Date: |
Wed, 2 Mar 2016 21:19:19 +0100 |
While tinkering with the new kvm-unit-tests framework for Power,
I discovered that a couple of SPRs are destroyed during migration.
We've got to define them in QEMU and make sure that they are
synchronized with the kernel to make sure that the register
contents are not lost.
The first patch introduces the new PSPB register from POWER8,
second patcch fixes the definition of the TAR register, and
the third patch (which has been taken from Ben's "Add native
POWER8 platform" patch series) introduces some missing
performance monitor registers.
Benjamin Herrenschmidt (1):
ppc: Add a few more P8 PMU SPRs
Thomas Huth (2):
ppc: Define the PSPB register on POWER8
ppc: Fix migration of the TAR SPR
target-ppc/cpu.h | 8 ++++++++
target-ppc/translate_init.c | 45 +++++++++++++++++++++++++++++++++++++++++----
2 files changed, 49 insertions(+), 4 deletions(-)
--
1.8.3.1
- [Qemu-devel] [PATCH 0/3] ppc: Define some more SPRs of POWER8 in QEMU to fix migration,
Thomas Huth <=